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Observer
Observer
469 Views
Registered: ‎05-10-2018

dram test failed on zcu106 rev1.0

i am using sdk2018.3 to test ps ddr on zcu106 rev1.0. The following is dram test log. there is no additional ouput to indicate the result. 

Enter Test Option:
0
Starting Memory Test...
16MB length - Address 0x0...
---------+--------+------------------------------------------------+-----------
TEST | ERROR | PER-BYTE-LANE ERROR COUNT | TIME
| COUNT | #0 , #1 , #2 , #3 , #4 , #5 , #6 , #7 | (sec)
---------+--------+------------------------------------------------+-----------

i also apply the patches from AR72113. But no improvement.

https://www.xilinx.com/support/answers/72113.html

It seems to be ps ddr problem.

BTW, simple application on ddr (like lwip) is okay

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4 Replies
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Xilinx Employee
Xilinx Employee
439 Views
Registered: ‎09-01-2014

Re: dram test failed on zcu106 rev1.0

Are you using a new DIMM ZCU106 board? if not, patch from AR#72113 is not needed.
Do you change the DDR setting in PCW? Like enable ECC?
We had issues in 2018.2, but all fixed in 2018.3
https://www.xilinx.com/support/answers/69298.html
https://www.xilinx.com/support/answers/72059.html
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Observer
Observer
422 Views
Registered: ‎05-10-2018

Re: dram test failed on zcu106 rev1.0

Hi, ritakur
ZCU106 is labeled 0432032-02 onward, so it is shipping with a new SODIMM.
The project is created via zcu106 board file in VIVADO 2018.3.
Simple application test like lwip is passed, except dram test. it maybe a bug.
BTW, manually change ddr setting in 2018.2, the dram test is okay.
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Xilinx Employee
Xilinx Employee
412 Views
Registered: ‎09-01-2014

Re: dram test failed on zcu106 rev1.0

Are you running FSBL first, then run DRAM test?
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Observer
Observer
396 Views
Registered: ‎05-10-2018

Re: dram test failed on zcu106 rev1.0

Hi, ritakur
I didn't run fsbl before dram test. I think this is the reason for current problem. psu_init use default setting in PCW, while fsbl will reconfigure the dimm parameters.
Thanks for your support.
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