09-10-2009 07:18 AM
Hi, i've a problem with edk 9.2 and a peripheral.
I use CIP wizard to create an empty template for my device, choosing XPS project to store the device. Than i open the project generated in \pcores to modify User_logic and insert my device, declaring a component, signals and creating a port mapping in the implementation section
component dsp_top is
dsp_rstn : in std_logic;
dsp_clk : in std_logic;
cic_clk : in std_logic;
cic_rstn : in std_logic;
When i try to synth. the project, everithing is ok, and no errors are generated, so re-importing the peripheral with CIP choosing "existing peripheral" seems to work. But when i try to generate bitstream i got error
Processing BMM file ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block
'dsp_test_0/dsp_test_0/USER_LOGIC_I/DSP_CORE' with type 'dsp_top'
could not be resolved. A pin name misspelling can cause this, a missing edif
or ngc file, or the misspelling of a type name. Symbol 'dsp_top' is not
supported in target 'virtex5'.
09-12-2009 12:20 AM
Please clean up the project once and then try to generate the bitstream.
Hopefully the issue will be resolved.
09-17-2009 01:58 AM
Tried...the device is now available because i've modified .mpd file and i've created the bbd file, but edk gives me some problem with mapping fase: during the generation of the dsp netlist, everithing is removed because i need to generate netlist file without i/o blocks, so the dsp is undriven and then simplified with an emtpy box..
How can i create netlist file without I/O blocks without simplifications??