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liuyz
Adventurer
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Registered: ‎01-13-2019

error building fsbl_a53 example in ug1209

I could not build fsbl_a53 example in Section 'Create First Stage Boot Loader for Arm Cortex-A53-Based APU' in ug1209 v2020.1.

The following error message come up:

 

Building target: fsbl_a53_zcu102.elf
Invoking: ARM v8 gcc linker
aarch64-none-elf-gcc -n -Wl,-T -Wl,../src/lscript.ld -L/mnt/data/SandBox/edt_zcu102_wrapper/export/edt_zcu102_wrapper/sw/edt_zcu102_wrapper/standalone_domain/bsplib/lib -o "fsbl_a53_zcu102.elf"  ./src/psu_init.o ./src/xfsbl_authentication.o ./src/xfsbl_board.o ./src/xfsbl_bs.o ./src/xfsbl_csu_dma.o ./src/xfsbl_ddr_init.o ./src/xfsbl_dfu_util.o ./src/xfsbl_exit.o ./src/xfsbl_handoff.o ./src/xfsbl_hooks.o ./src/xfsbl_image_header.o ./src/xfsbl_initialization.o ./src/xfsbl_main.o ./src/xfsbl_misc.o ./src/xfsbl_misc_drivers.o ./src/xfsbl_nand.o ./src/xfsbl_partition_load.o ./src/xfsbl_plpartition_valid.o ./src/xfsbl_qspi.o ./src/xfsbl_rsa_sha.o ./src/xfsbl_sd.o ./src/xfsbl_translation_table.o ./src/xfsbl_usb.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilpm,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilsecure,-lxil,-lgcc,-lc,--end-group
/mnt/data/XilinxTools/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: address 0xfffe9e18 of fsbl_a53_zcu102.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
/mnt/data/XilinxTools/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: address 0xfffe9e18 of fsbl_a53_zcu102.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
/mnt/data/XilinxTools/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: address 0xfffe9e18 of fsbl_a53_zcu102.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
/mnt/data/XilinxTools/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: section .handoff_params VMA [00000000fffe9e00,00000000fffe9e87] overlaps section .dup_data VMA [00000000fffe8c00,00000000fffe9e17]
collect2.real: error: ld returned 1 exit status
make: *** [makefile:38: fsbl_a53_zcu102.elf] Error 1

 

The hardware platform is zcu102 and it was created follow the process in Chapter 2 of the same document (ug1209).

The Vitis and Vivado are all v2020.1.

No problem to follow the other examples in Chapter 3 that using the same zcu102 xsa.

Thanks for help.

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nsullivan
Contributor
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717 Views
Registered: ‎10-08-2018

Those messages look like the ones you see when the FSBL is too big to fit in on-chip RAM.  Did you enable debug in the FSBL, or change any other settings?


Nathan Sullivan - Senior Embedded Software Engineer - www.designlinxhs.com
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liuyz
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Registered: ‎01-13-2019

The debug was enabled in the example, but the optimisation flags also added.

Since I just following the ug1209 official guide on zcu102 which was requrest in the tutorial, I didn't expect to receive these kind of errors.

By the way, I also tried the example on zcu111 platform, and there is NO such errors. All went through.

I think you are right. It seems that the zcu102 do not have enough FSBL RAM space to complete the example in the tutorial.

Please correct me if I missed anything here.

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marcb
Moderator
Moderator
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Registered: ‎05-08-2012

Hi @liuyz 

Can you see if the following helps?

https://forums.xilinx.com/t5/Embedded-Development-Tools/Building-quot-Zynq-MP-FSBL-quot-application-project-on-ZCU104/m-p/1147341

 

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liuyz
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Registered: ‎01-13-2019

hi @marcb ,

 

The .dup_data section is available in the lscript.ld by default. And it is allocated to psu_ocm_ram_0_S_AXI_BASEADDR.

It is defined as

.dup_data (ALIGN(64)): {
   __dup_data_start = .;
   . += __data_end - __data_start ;
   __dup_data_end = .;
} > psu_ocm_ram_0_S_AXI_BASEADDR

and the memory regin is defined as 

MEMORY
{
   psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x00029D00
   psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFE9E00, LENGTH = 0x00000200
   psu_ocm_ram_2_S_AXI_BASEADDR : ORIGIN = 0xFFFF0040, LENGTH = 0x0000FDC0

}

Also,

_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 1024;

These are all default values when following the ug1209 tutorial.

Please let me know where could be the problem. Thanks.

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marcb
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Registered: ‎05-08-2012

Hi @liuyz 

Can you upload the exported Vitis archive to allow the community to help further? Also, what operating system is Vitis installed on?

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liuyz
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Registered: ‎01-13-2019

Hi @marcb ,

I created FSBL with ZCU111 and the errors are gone.

To reproduce the errors, just follow the tutorial ug1209 and ZCU102.

Basically, same procedure for ZCU111 is okay, for ZCU102 will report errors.

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marcb
Moderator
Moderator
437 Views
Registered: ‎05-08-2012

Hi @liuyz 

Was this done on a Windows machine? I didn't see the errors using Linux while building the platform for chapter 3 of UG1209.

Did you happen to reset the BSP sources, or update the XSA?

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liuyz
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Registered: ‎01-13-2019

Hi @marcb ,

I'm on RHEL 7.6.

I didn't reset the BSP or update the XSA.

Are you running on RHEL or Ubuntu? ZCU111 or ZCU102?

Thanks a lot.

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liuyz
Adventurer
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Registered: ‎01-13-2019

hi @marcb ,

After exclude the NAND and QSPI boots and SECURE feature, I can now build the fsbl_a53 example.

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