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Observer clmnt_lbrr
Observer
10,732 Views
Registered: ‎05-28-2015

export hardware flow is not supported for design with no block diagram instances

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Hi every one,

 

During my internship I work on a project started by someone else. I've made lot of tutorial in order to understand how vivado and the SDK works, but on this project the simple feature of exporting hardware doesn't work...

 

If you have any idea of answer that would be helpfull.

 

I have attached a screenshot of the error.

 

clmnt_lbrr

 

Vivado version: 2014.4

Board: KC705

 

Screenshot-1.png
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1 Solution

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Moderator
Moderator
19,331 Views
Registered: ‎07-31-2012

Re: export hardware flow is not supported for design with no block diagram instances

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Hi,

 

Please assemble the mcs, clock generator and other IPs in an IPI project i.e. block design and have the RTL logic wrapper around it if any. Then the tool will detect the block design and will export to SDK.

Refer to page 71 in http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug940-vivado-tutorial-embedded-design.pdf 

 

Regards

Praveen

 

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15 Replies
Xilinx Employee
Xilinx Employee
10,716 Views
Registered: ‎10-24-2013

Re: export hardware flow is not supported for design with no block diagram instances

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Hi,
Please check the below thread.
http://forums.xilinx.com/t5/Embedded-Development-Tools/Vivado-2014-2-can-t-export-to-SDK/td-p/480754
Thanks,Vijay
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Scholar austin
Scholar
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Registered: ‎02-27-2008

Re: export hardware flow is not supported for design with no block diagram instances

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Please post your log file.  It will contain the reasons why you get this error.

 

And, read the last post in the thread suggested above.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer clmnt_lbrr
Observer
10,705 Views
Registered: ‎05-28-2015

Re: export hardware flow is not supported for design with no block diagram instances

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here is the log file,

 

#-----------------------------------------------------------
# Vivado v2014.4 (64-bit)
# SW Build 1067303 on Wed Nov 12 17:04:19 MST 2014
# IP Build 1068446 on Thu Nov 13 19:40:58 MST 2014
# Start of session at: Tue Jun  2 16:37:00 2015
# Process ID: 17119
# Log file: /user/erasmus/cluberry/vivado.log
# Journal file: /user/erasmus/cluberry/vivado.jou
#-----------------------------------------------------------
start_gui
open_project /user/erasmus/cluberry/Desktop/project/fin-math/workspaces/complete_dp/complete_dp.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/cadtools/xilinx/2010/Vivado/2014.4/data/ip'.
open_project: Time (s): cpu = 00:00:18 ; elapsed = 00:00:12 . Memory (MB): peak = 5751.062 ; gain = 71.664 ; free physical = 1921 ; free virtual = 18939
ERROR: [Vivado 12-4157] Export Hardware flow is not supported for designs with no block diagram instances

 

 

I've already seen this topic, but it is not speaking about the same error

 

clmnt_lbrr

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Observer clmnt_lbrr
Observer
10,693 Views
Registered: ‎05-28-2015

Re: export hardware flow is not supported for design with no block diagram instances

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Moreover, the implementation is completed but with time constrains errors...

 

Here is attached the log file of the Systhesis and Implementation if it could help

 

clmnt_lbrr

 

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Moderator
Moderator
19,332 Views
Registered: ‎07-31-2012

Re: export hardware flow is not supported for design with no block diagram instances

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Hi,

 

Please assemble the mcs, clock generator and other IPs in an IPI project i.e. block design and have the RTL logic wrapper around it if any. Then the tool will detect the block design and will export to SDK.

Refer to page 71 in http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug940-vivado-tutorial-embedded-design.pdf 

 

Regards

Praveen

 

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Observer clmnt_lbrr
Observer
10,687 Views
Registered: ‎05-28-2015

Re: export hardware flow is not supported for design with no block diagram instances

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So I should make a block with mcs and clockgen, and make a wrapper of a wrapper? Or should I just make a block design with the mcs, clockgen and the pricer's file?

 

clmnt_lbrr

 

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Moderator
Moderator
10,671 Views
Registered: ‎07-31-2012

Re: export hardware flow is not supported for design with no block diagram instances

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Hi,

 

I meant block design. 

 

Regards

Praveen

 

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Observer clmnt_lbrr
Observer
10,667 Views
Registered: ‎05-28-2015

Re: export hardware flow is not supported for design with no block diagram instances

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ok, but can we do a block design from file that are already under a wrapper. A kind of "select the 3 files" -> right clic -> creat a block design?

 

clmnt_lbrr

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Observer clmnt_lbrr
Observer
10,620 Views
Registered: ‎05-28-2015

Re: export hardware flow is not supported for design with no block diagram instances

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@pvenugo wrote:

Hi,

 

Please assemble the mcs, clock generator and other IPs in an IPI project i.e. block design and have the RTL logic wrapper around it if any. Then the tool will detect the block design and will export to SDK.

Refer to page 71 in http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug940-vivado-tutorial-embedded-design.pdf 



I think it's the good way to solve the problem but I need to make lot of modifications to the project as it is now, I'll send you feedback when that would have been done.

 

clmnt_lbrr

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Observer clmnt_lbrr
Observer
9,009 Views
Registered: ‎05-28-2015

Re: export hardware flow is not supported for design with no block diagram instances

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Hi,

 

Since the last time I have change the structure of the project as @pvenugo advised me.

 

I now have no problem to export, at least to windows shows up in vivado, but the SDK doesn't open as it should be

 

here is the picture of the structure and the SDK problem

 

Screenshot-4.png

 

Screenshot-3.png

 

It seems that no hardware are exported, do you see anything not normal?

 

clmnt_lbrr

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Observer clmnt_lbrr
Observer
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Registered: ‎05-28-2015

Re: export hardware flow is not supported for design with no block diagram instances

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So I have open an other project Vivado and SDK it was working. I have retry the first project and it work now...

clmnt_lbrr
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Moderator
Moderator
8,987 Views
Registered: ‎07-31-2012

Re: export hardware flow is not supported for design with no block diagram instances

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Hi,

 

So, did you get the design work and exported to SDK without any issue?

 

Regards

Praveen


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Observer clmnt_lbrr
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Registered: ‎05-28-2015

Re: export hardware flow is not supported for design with no block diagram instances

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Hi,

Yes the design seems to work (I have others things to check which are not relative to this section), I managed to export to SDK and programed the board without others problems than describe in my posts.

note : I have update Vivado to 2015.1 during the redevelopment of the project, if it has a importance for future reader.

clmnt_lbrr

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Moderator
Moderator
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Registered: ‎07-31-2012

Re: export hardware flow is not supported for design with no block diagram instances

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OK, if this post has solved your issue, please mark it as accepted solution.

Regards
Praveen

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Observer clmnt_lbrr
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Registered: ‎05-28-2015

Re: export hardware flow is not supported for design with no block diagram instances

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already done!

clmnt_lbrr
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