I am experimenting with the mutex IP core in the Xilinx library. I would like to know if there are any fairness guarantees among the available bus (PLB) connections. I've implemented an eight core Microblaze design where each core connects through a dedicated bus line to the mutex and there appears to be random starvation of cores (between re-runs).
Is that indented as normal operation by design? Should fairness be handled at another level, e.g. using a shared bus to connect all cores to the mutex?