generate bitstream error

[mpanchal]

I am trying to implement simple design in xps 11.1 but when i am going for generate bitstream it is giving me following error. Please give some solution

Place:713 - IOB component "fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13>" and IODELAY component "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g en_dq[13].u_iob_dq/u_idelay_dq" must be placed adjacent to each other into the same I/O tile in order to route net "DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/g en_dq[13].u_iob_dq/dq_in".

The following issue has been detected: Some of the logic associated with this structure is locked. This should cause the rest of the logic to be locked.A problem was found at site IODELAY_X0Y56 where we must place IODELAY DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge n_dq[13].u_iob_dq/u_idelay_dq in order to satisfy the relative placement requirements of this logic.

IODELAY DDR2_SDRAM/DDR2_SDRAM/mpmc_core_0/gen_v5_ddr2_phy.mpmc_phy_if_0/u_phy_io_0/ge n_dqs[0].u_iob_dqs/u_iodelay_dq_ce appears to already be placed there which makes this design unplaceable.

 make: *** [__xps/ml505_bsb_system_routed] Error 1

[dcherry]

Is this a MIG compatible DDR2 design or a custom PHY interface?

[lvcargnini]

I'm having the same issue using the DDR2 IP for XUPV5-ML509 board, and the problem seems related to the UCF file.

Because when using PlanAhead running the DRC verification it report a problem caused by the UCF too. 

I tried using the sample design projects for this board, and creating from scratch ALL stoped in the same error (of course from scratch using the board configuration files for EDK, supplied in the Xilinx web-site).

Message Edited by lvcargnini on 03-11-2010 08:43 AM

[dcherry]

Did you run through MIG to create the constraints since this will be required when using a MIG compatible DDR2 pinout? This is described in the MPMC data sheet.