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Adventurer
Adventurer
6,711 Views
Registered: ‎05-22-2009

generate for OS'es, Drivers and Libraries -> error: Number of interrupt inputs

Hello,

 

I have a working design in my XPS. There is a custom generated IP which connect the PLB to a BRAM and has a interrupt control with one interrupt. The software I already have written was running well.

 

Now, I wont to add a  Interrupt Controller (xps_intc_1.00.a) in the XPS. I have generated new addresses too. But when I "generate libraries and BSPs", I get this error messages. How can I change the faulty interrupt size and which size is the right size?

The properties of the interrupt controller have the option "Auto computed" for "number of Interrupt Inputs".

 


Running generate for OS'es, Drivers and Libraries ...
ERROR:MDT - intc () - Internal error: Number of interrupt inputs on xps_intc_0
   (1) is not the same as length of total number of interrupt sources (0). If
   any interrupt source is a vector then libgen does not support this use case
       while executing
   "error "Internal error: Number of interrupt inputs on $periph_name
   ($num_intr_inputs) is not the same as length of total number of interrupt
   sources ([..."
       (procedure "intc_define_vector_table" line 13)
       invoked from within
   "intc_define_vector_table $periph $config_inc $tmp_config_file"
       (procedure "intc_define_config_file" line 46)
       invoked from within
   "intc_define_config_file $drv_handle $periphs $config_inc"
       (procedure "::sw_intc_v1_11_a::generate" line 23)
       invoked from within
   "::sw_intc_v1_11_a::generate 43778272"
ERROR:MDT - Error while running "generate" for processor ppc440_0...
make: *** [ppc440_0/lib/libxil.a] Error 2

 

 

I am using the XPS  10.1

Thank you for help.

Message Edited by hwfgjdsd on 06-03-2009 02:48 AM
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8 Replies
6,707 Views
Registered: ‎08-21-2008

Re: generate for OS'es, Drivers and Libraries -> error: Number of interrupt inputs

Hello. 

Can you paste your MHS file for reference....

Best of luck.
--
Unlimited in my Limits.
0 Kudos
Adventurer
Adventurer
6,705 Views
Registered: ‎05-22-2009

Re: generate for OS'es, Drivers and Libraries -> error: Number of interrupt inputs


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Mon May 25 14:46:43 2009
# Target Board:  Xilinx Virtex 5 ML507 Evaluation Platform Rev A
# Family:    virtex5
# Device:    xc5vfx70t
# Package:   ff1136
# Speed Grade:  -1
# Processor: ppc440_0
# Processor clock frequency: 400.00 MHz
# Bus clock frequency: 100.00 MHz
# On Chip Memory :  16 KB
# Total Off Chip Memory :   1 MB
# - SRAM =   1 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
 PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO, DIR = IO, VEC = [0:7]
 PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO, DIR = IO, VEC = [0:4]
 PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO, DIR = IO, VEC = [0:7]
 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [7:30]
 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3]
 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O
 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O
 PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O
 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O
 PORT fpga_0_SRAM_CLK = ZBT_CLK_OUT_s, DIR = O
 PORT fpga_0_SRAM_CLK_FB = ZBT_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST


BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_APU_CONTROL = 0b00000000000000001
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE MFCB = fcb_v20_0
 BUS_INTERFACE JTAGPPC = jtagppc_cntlr_0_0
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC440CLK = proc_clk_s
 PORT CPMPPCMPLBCLK = sys_clk_s
 PORT CPMPPCS0PLBCLK = sys_clk_s
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT CPMINTERCONNECTCLK = ppc440_0_CPMINTERCONNECTCLK
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_0
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER HW_VER = 1.03.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER C_SPLB_P2P = 0
 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xffffc000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
END

BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO
END

BEGIN xps_gpio
 PARAMETER INSTANCE = Push_Buttons_5Bit
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x81420000
 PARAMETER C_HIGHADDR = 0x8142ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO
END

BEGIN xps_gpio
 PARAMETER INSTANCE = DIP_Switches_8Bit
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x81440000
 PARAMETER C_HIGHADDR = 0x8144ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = SRAM
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
 PARAMETER C_SYNCH_MEM_0 = 1
 PARAMETER C_TCEDV_PS_MEM_0 = 0
 PARAMETER C_TWC_PS_MEM_0 = 0
 PARAMETER C_TAVDV_PS_MEM_0 = 0
 PARAMETER C_TWP_PS_MEM_0 = 0
 PARAMETER C_THZCE_PS_MEM_0 = 0
 PARAMETER C_THZOE_PS_MEM_0 = 0
 PARAMETER C_TLZWE_PS_MEM_0 = 0
 PARAMETER C_MEM0_BASEADDR = 0x00000000
 PARAMETER C_MEM0_HIGHADDR = 0x000fffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT Mem_A = fpga_0_SRAM_Mem_A_split
 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN
 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN
 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN
 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ
 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN
 PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN
 PORT RdClk = sys_clk_s
END

BEGIN util_bus_split
 PARAMETER INSTANCE = SRAM_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 7
 PARAMETER C_SPLIT = 31
 PORT Sig = fpga_0_SRAM_Mem_A_split
 PORT Out1 = fpga_0_SRAM_Mem_A
END

BEGIN fcb_v20
 PARAMETER INSTANCE = fcb_v20_0
 PARAMETER HW_VER = 1.00.a
 PORT SYS_RST = sys_bus_reset
 PORT FCB_CLK = fcm_clk_s
END

BEGIN apu_fpu_virtex5
 PARAMETER INSTANCE = apu_fpu_virtex5_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DOUBLE_PRECISION = 1
 PARAMETER C_USE_RLOCS = 0
 PARAMETER C_LATENCY_CONF = 1
 BUS_INTERFACE SFCB2 = fcb_v20_0
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 400000000
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = PLL0
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT3_FREQ = 133333333
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = PLL0_ADJUST
 PARAMETER C_CLKFBIN_FREQ = 100000000
 PARAMETER C_CLKFBOUT_FREQ = 100000000
 PARAMETER C_CLKFBOUT_BUF = TRUE
 PORT CLKOUT0 = proc_clk_s
 PORT CLKOUT1 = ppc440_0_CPMINTERCONNECTCLK
 PORT CLKOUT2 = sys_clk_s
 PORT CLKOUT3 = fcm_clk_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
 PORT CLKFBIN = ZBT_CLK_FB_s
 PORT CLKFBOUT = ZBT_CLK_OUT_s
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_0
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = jtagppc_cntlr_0_0
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN plb2wb
 PARAMETER INSTANCE = plb2wb_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0xc6400000
 PARAMETER C_HIGHADDR = 0xc640ffff
 PARAMETER C_MEM0_BASEADDR = 0xc7e00000
 PARAMETER C_MEM0_HIGHADDR = 0xc7e0ffff
 BUS_INTERFACE SPLB = plb_v46_1
END

BEGIN plbv46_plbv46_bridge
 PARAMETER INSTANCE = plbv46_plbv46_bridge_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_RNG1_BASEADDR = 0xC8000000
 PARAMETER C_RNG1_HIGHADDR = 0xC9FFFFFF
 PARAMETER C_BRIDGE_BASEADDR = 0x86200000
 PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff
 PARAMETER C_RNG0_BASEADDR = 0xc6000000
 PARAMETER C_RNG0_HIGHADDR = 0xc7ffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE MPLB = plb_v46_1
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_1
 PARAMETER HW_VER = 1.03.a
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = plb_v46_0
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = plb_v46_0
END
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6,702 Views
Registered: ‎08-21-2008

Re: generate for OS'es, Drivers and Libraries -> error: Number of interrupt inputs

Hello.

In your MHS file i can't see any interrupts being used along with any IP. Neither the xps_intc at the last of your MHS file shows any interrupts being used. How many number of interrupts intc is showing if you go for configure IP of that particular block. Also do one thing open the ports corresponding to intc IP and see if it is showing any interrupt being used in your design.

Best of luck.
--
Unlimited in my Limits.
0 Kudos
6,686 Views
Registered: ‎08-21-2008

Re: generate for OS'es, Drivers and Libraries -> error: Number of interrupt inputs

If you have to instantiate interrupt IP then you have to enable interrupt in any IP of your choice according to your requirement either in RS232 or push button or dip switch and then accordingly you have map this interrupt in xps_intc (ports) and simultaneously write a service routine on the software side to manage the interrupt. Hope it helps.
Best of luck.
--
Unlimited in my Limits.
0 Kudos
Adventurer
Adventurer
6,685 Views
Registered: ‎05-22-2009

Re: generate for OS'es, Drivers and Libraries -> error: Number of interrupt inputs

. Thank you prateek_bhatt,

 

your suspicion was right. There was no connection between the xps_intc and my added IPs. Now I add all potential interrupt connections and add a new connection for Irq-output (now that is xps_intc_0_Irq). So I get this mhs file.

 

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Mon May 25 14:46:43 2009
# Target Board:  Xilinx Virtex 5 ML507 Evaluation Platform Rev A
# Family:    virtex5
# Device:    xc5vfx70t
# Package:   ff1136
# Speed Grade:  -1
# Processor: ppc440_0
# Processor clock frequency: 400.00 MHz
# Bus clock frequency: 100.00 MHz
# On Chip Memory :  16 KB
# Total Off Chip Memory :   1 MB
# - SRAM =   1 MB
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
 PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO, DIR = IO, VEC = [0:7]
 PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO, DIR = IO, VEC = [0:4]
 PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO, DIR = IO, VEC = [0:7]
 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [7:30]
 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3]
 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O
 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O
 PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O
 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O
 PORT fpga_0_SRAM_CLK = ZBT_CLK_OUT_s, DIR = O
 PORT fpga_0_SRAM_CLK_FB = ZBT_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST


BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_APU_CONTROL = 0b00000000000000001
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE MFCB = fcb_v20_0
 BUS_INTERFACE JTAGPPC = jtagppc_cntlr_0_0
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC440CLK = proc_clk_s
 PORT CPMPPCMPLBCLK = sys_clk_s
 PORT CPMPPCS0PLBCLK = sys_clk_s
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT CPMINTERCONNECTCLK = ppc440_0_CPMINTERCONNECTCLK
 PORT PPCEICINTERCONNECTIRQ = ppc440_0_PPCEICINTERCONNECTIRQ
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_0
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER HW_VER = 1.03.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
 PORT Bus_Error_Det = plb_v46_0_Bus_Error_Det
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER C_SPLB_P2P = 0
 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xffffc000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT RX = fpga_0_RS232_Uart_1_RX
 PORT TX = fpga_0_RS232_Uart_1_TX
 PORT Interrupt = RS232_Uart_1_Interrupt
END

BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO
END

BEGIN xps_gpio
 PARAMETER INSTANCE = Push_Buttons_5Bit
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x81420000
 PARAMETER C_HIGHADDR = 0x8142ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO
END

BEGIN xps_gpio
 PARAMETER INSTANCE = DIP_Switches_8Bit
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x81440000
 PARAMETER C_HIGHADDR = 0x8144ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = SRAM
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
 PARAMETER C_SYNCH_MEM_0 = 1
 PARAMETER C_TCEDV_PS_MEM_0 = 0
 PARAMETER C_TWC_PS_MEM_0 = 0
 PARAMETER C_TAVDV_PS_MEM_0 = 0
 PARAMETER C_TWP_PS_MEM_0 = 0
 PARAMETER C_THZCE_PS_MEM_0 = 0
 PARAMETER C_THZOE_PS_MEM_0 = 0
 PARAMETER C_TLZWE_PS_MEM_0 = 0
 PARAMETER C_MEM0_BASEADDR = 0x00000000
 PARAMETER C_MEM0_HIGHADDR = 0x000fffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT Mem_A = fpga_0_SRAM_Mem_A_split
 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN
 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN
 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN
 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ
 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN
 PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN
 PORT RdClk = sys_clk_s
END

BEGIN util_bus_split
 PARAMETER INSTANCE = SRAM_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 7
 PARAMETER C_SPLIT = 31
 PORT Sig = fpga_0_SRAM_Mem_A_split
 PORT Out1 = fpga_0_SRAM_Mem_A
END

BEGIN fcb_v20
 PARAMETER INSTANCE = fcb_v20_0
 PARAMETER HW_VER = 1.00.a
 PORT SYS_RST = sys_bus_reset
 PORT FCB_CLK = fcm_clk_s
END

BEGIN apu_fpu_virtex5
 PARAMETER INSTANCE = apu_fpu_virtex5_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DOUBLE_PRECISION = 1
 PARAMETER C_USE_RLOCS = 0
 PARAMETER C_LATENCY_CONF = 1
 BUS_INTERFACE SFCB2 = fcb_v20_0
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 400000000
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = PLL0
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT3_FREQ = 133333333
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = PLL0_ADJUST
 PARAMETER C_CLKFBIN_FREQ = 100000000
 PARAMETER C_CLKFBOUT_FREQ = 100000000
 PARAMETER C_CLKFBOUT_BUF = TRUE
 PORT CLKOUT0 = proc_clk_s
 PORT CLKOUT1 = ppc440_0_CPMINTERCONNECTCLK
 PORT CLKOUT2 = sys_clk_s
 PORT CLKOUT3 = fcm_clk_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
 PORT CLKFBIN = ZBT_CLK_FB_s
 PORT CLKFBOUT = ZBT_CLK_OUT_s
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_0
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = jtagppc_cntlr_0_0
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 0
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN plb2wb
 PARAMETER INSTANCE = plb2wb_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0xc6400000
 PARAMETER C_HIGHADDR = 0xc640ffff
 PARAMETER C_MEM0_BASEADDR = 0xc7e00000
 PARAMETER C_MEM0_HIGHADDR = 0xc7e0ffff
 BUS_INTERFACE SPLB = plb_v46_1
 PORT IP2INTC_Irpt = plb2wb_0_IP2INTC_Irpt
END

BEGIN plbv46_plbv46_bridge
 PARAMETER INSTANCE = plbv46_plbv46_bridge_0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_RNG1_BASEADDR = 0xC8000000
 PARAMETER C_RNG1_HIGHADDR = 0xC9FFFFFF
 PARAMETER C_BRIDGE_BASEADDR = 0x86200000
 PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff
 PARAMETER C_RNG0_BASEADDR = 0xc6000000
 PARAMETER C_RNG0_HIGHADDR = 0xc7ffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE MPLB = plb_v46_1
 PORT IP2INTC_Irpt = plbv46_plbv46_bridge_0_IP2INTC_Irpt
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_1
 PARAMETER HW_VER = 1.03.a
 PORT Bus_Error_Det = plb_v46_1_Bus_Error_Det
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x83c00000
 PARAMETER C_HIGHADDR = 0x83c0ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT Interrupt = xps_timer_0_Interrupt
END

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT Intr = plbv46_plbv46_bridge_0_IP2INTC_Irpt&RS232_Uart_1_Interrupt&plb_v46_1_Bus_Error_Det&plb_v46_0_Bus_Error_Det&xps_timer_0_Interrupt&plb2wb_0_IP2INTC_Irpt&ppc440_0_PPCEICINTERCONNECTIRQ
 PORT Irq = xps_intc_0_Irq
END

 

 

 

 

 

 

 

It seems that everything is ok now. But although I get thie output while generating the libraries:

...

Check port drivers...

WARNING:MDT - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -

   D:\xxx\sw\ppc\yyy\system.mhs line 241 - floating connection!

WARNING:MDT - PORT:Irq CONNECTOR:xps_intc_0_Irq -

   D:\xxx\sw\ppc\yyy\system.mhs line 292 - floating connection!

 

Performing Clock DRCs...

 

INFO:MDT - List of peripherals addressable from processor instance ppc440_0 :

  - xps_bram_if_cntlr_1

  - RS232_Uart_1

  - LEDs_8Bit

  - Push_Buttons_5Bit

  - DIP_Switches_8Bit

  - SRAM

  - plbv46_plbv46_bridge_0

  - plb2wb_0

  - xps_timer_0

  - xps_intc_0

  - apu_fpu_virtex5_0

 

Building Directory Structure for ppc440_0

...

 

Message Edited by hwfgjdsd on 06-03-2009 06:38 AM
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Registered: ‎08-21-2008

Re: generate for OS'es, Drivers and Libraries -> error: Number of interrupt inputs

Hello.

In the ports section go for xps_intc and expand it.

In the INTR drop down menu map all the interrupts that you have enabled (UART and Timer).

In the IRQ drop down menu select interrupt or go for new connection which will give you interrupt.

Then your hardware will be complete. Hope that helps. 

Message Edited by prateek_bhatt on 06-03-2009 06:40 AM
Best of luck.
--
Unlimited in my Limits.
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Adventurer
Adventurer
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Registered: ‎05-22-2009

Re: generate for OS'es, Drivers and Libraries -> error: Number of interrupt inputs

By the way:

system.mhs line 241:
 PORT Peripheral_Reset = sys_periph_reset

 

system.mhs line 292:

PORT Irq = xps_intc_0_Irq

Message Edited by hwfgjdsd on 06-03-2009 06:38 AM
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6,674 Views
Registered: ‎08-21-2008

Re: generate for OS'es, Drivers and Libraries -> error: Number of interrupt inputs

Hello.

I have edited message 7 and attached one document. Go through it. It shows the mapping that you have to do. Yes what you have shown is correct. 

Best of luck.
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Unlimited in my Limits.
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