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Observer
Observer
13,084 Views
Registered: ‎10-04-2007

help me about EDK

Please help me ,thank you
There are  "opb_tsd_ref_v1_00_a" and opb_pci_ref_v1_00_b in pcores directory ,and there are "touchscreen_ref_v1_00_a" and "pci_ref_v1_00_b" in drivers directory




my project in XPS



ADDRESS



completed code C for project---->build project------->
---------------------------------------------------------------------------------------------------------------------------
Running CopyFiles ...


Copying files for os standalone_v1_00_a from

C:\EDK\sw\lib\bsp\standalone_v1_00_a\src\ to


C:\thanh\ppc405_0\libsrc\standalone_v1_00_a\ ...


Copying files for driver uartlite_v1_00_b from

C:\EDK\sw\XilinxProcessorIPLib\drivers\uartlite_v1_00_b\src\ to


C:\thanh\ppc405_0\libsrc\uartlite_v1_00_b\ ...


Copying files for driver gpio_v2_00_a from


C:\EDK\sw\XilinxProcessorIPLib\drivers\gpio_v2_00_a\src\ to


C:\thanh\ppc405_0\libsrc\gpio_v2_00_a\ ...


Copying files for driver sysace_v1_00_a from


C:\EDK\sw\XilinxProcessorIPLib\drivers\sysace_v1_00_a\src\ to


C:\thanh\ppc405_0\libsrc\sysace_v1_00_a\ ...


Copying files for driver intc_v1_00_c from


C:\EDK\sw\XilinxProcessorIPLib\drivers\intc_v1_00_c\src\ to


C:\thanh\ppc405_0\libsrc\intc_v1_00_c\ ...
Copying files for driver ddr_v1_00_b from


C:\EDK\sw\XilinxProcessorIPLib\drivers\ddr_v1_00_b\src\ to


C:\thanh\ppc405_0\libsrc\ddr_v1_00_b\ ...


Copying files for driver cpu_ppc405_v1_00_a from


C:\EDK\sw\XilinxProcessorIPLib\drivers\cpu_ppc405_v1_00_a\src\ to


C:\thanh\ppc405_0\libsrc\cpu_ppc405_v1_00_a\ ...
Running DRCs for OSes, Drivers and Libraries ...


Running generate for OS'es, Drivers and Libraries .

--------------------------------------------------------------------------------------------------------------------------

YOU CAN TELL ME WHY XPS DON'T COPY DRIVER "touchscreen_ref_v1_00_a" from DRIVERS DIRECTORY to C:\thanh\ppc405_0\libsrc\cpu_ppc405_v1_00_a\ ...AND MY PROJECT APPEAR ERROR BECAUSE XPS DON'T COPY "touchscreen_ref_v1_00_a" ...
-------------------------------------------------------------------------------------------------
touchscreen_int/src/touchscreen_int.c:34:26: xtouchscreen.h: No such file or directory


touchscreen_int/src/touchscreen_int.c: In function `main':


touchscreen_int/src/touchscreen_int.c:103: error: `XPAR_OPB_UART16550_0_BASEADDR' undeclared (first use in this function)


touchscreen_int/src/touchscreen_int.c:103: error: (Each undeclared identifier is reported only once


touchscreen_int/src/touchscreen_int.c:103: error: for each function it appears in.)


...........................
---------------------------------------------------------------------------------------------------------

I SEE THIS WARNING WHEN COMPILING


---------------------------------------------------------------------------------------------------------------------
WARNING
:MDT - Peripheral opb_tsd_ref_0 is not connected to any of the processors


in the system. Check for the following reasons.


1. opb_tsd_ref_0 is not connected to any of the buses connected to a


processor.


2. opb_tsd_ref_0 does not have adresses set correctly.


3. opb_tsd_ref_0's address is not within any of the bridge windows connected


to a processor.


---------------------------------------------------------------------------



PLEASE SHOW ME HOW SOLVE THIS PROBLEM .THANK YOU

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Xilinx Employee
Xilinx Employee
13,065 Views
Registered: ‎08-06-2007

Hi,
 
How does your system.mhs file look like?
How is the IP connected?
 
Göran Bilski
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Observer
Observer
13,054 Views
Registered: ‎10-04-2007

MY SYSTEM.MHS
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
PARAMETER VERSION = 2.1.0
PORT fpga_0_DDR_SDRAM_32Mx32_DDR_Clk_pin = fpga_0_DDR_SDRAM_32Mx32_DDR_Clk, DIR = OUTPUT
 .
 .
 .
PORT PCI_INTD = PCI_INTD, DIR = I

BEGIN plb_v34
 PARAMETER INSTANCE = plb
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DCR_INTFCE = 1
 PARAMETER C_EXT_RESET_HIGH = 1
 BUS_INTERFACE SDCR = dcr_v29_0
 PORT SYS_Rst = sys_bus_reset
 PORT PLB_Clk = sys_clk_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_USE_LUT_OR = 0
 PORT SYS_Rst = sys_bus_reset
 PORT OPB_Clk = sys_clk_s
END

BEGIN plb2opb_bridge
 PARAMETER INSTANCE = plb2opb
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DCR_INTFCE = 1
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_RNG0_BASEADDR = 0x40000000
 PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
 PARAMETER C_DCR_BASEADDR = 0b0000000000
 PARAMETER C_DCR_HIGHADDR = 0b0000000111
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE MOPB = opb
 PORT PLB_Clk = sys_clk_s
 PORT OPB_Clk = sys_clk_s
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 .
 .
 PORT TX = fpga_0_RS232_Uart_1_TX
END

BEGIN plb_ddr
 PARAMETER INSTANCE = DDR_SDRAM_32Mx32
 .
 .
 .
 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END


BEGIN opb_gpio
 PARAMETER INSTANCE = Push_Buttons_16Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 16
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 1
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_s
 PORT IP2INTC_Irpt = Push_Buttons_16Bit_IP2INTC_Irpt
 PORT GPIO_IO = fpga_0_Push_Buttons_16Bit_GPIO_IO
END

BEGIN opb_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 .
 .
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
END



BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = opb
 PORT Irq = EICC405EXTINPUTIRQ
 PORT Intr = PCI_INTR_OUT & TSD_intr & DDR_SDRAM_32Mx32_IP2INTC_Irpt & RS232_Uart_1_Interrupt & SysACE_CompactFlash_SysACE_IRQ & LEDs_16Bit_IP2INTC_Irpt & Push_Buttons_16Bit_IP2INTC_Irpt
END

BEGIN util_reduced_logic
 PARAMETER INSTANCE = ORGate_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_OPERATION = or
 PARAMETER C_SIZE = 2
 PORT Op1 = sys_rst_s & 0b0
 PORT Res = fpga_0_ORGate_1_Res
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 .
 .
 .
 PORT LOCKED = dcm_0_lock
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK270_BUF = TRUE
 PARAMETER C_CLK90_BUF = TRUE
 PARAMETER C_CLKIN_PERIOD = 10.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_CLKDV_DIVIDE = 200
 PARAMETER C_CLKDV_BUF = TRUE
 PORT CLKIN = ddr_feedback_s
 PORT CLK90 = ddr_clk_90_s
 PORT CLK270 = ddr_clk_90_n_s
 PORT CLK0 = dcm_1_FB
 PORT CLKFB = dcm_1_FB
 PORT RST = dcm_0_lock
 PORT LOCKED = dcm_1_lock
 PORT CLKDV = PCI_CLK
END

BEGIN opb2dcr_bridge
 PARAMETER INSTANCE = opb2dcr_bridge_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xd0000000
 PARAMETER C_HIGHADDR = 0xd0000fff
 BUS_INTERFACE SOPB = opb
 BUS_INTERFACE MDCR = dcr_v29_0
END

BEGIN dcr_intc
 PARAMETER INSTANCE = dcr_intc_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0b1111110000
 PARAMETER C_HIGHADDR = 0b1111110111
 PARAMETER C_U_SET = intc
 PARAMETER C_HAS_IPR = 0
 PARAMETER C_HAS_SIE = 0
 PARAMETER C_HAS_CIE = 0
 PARAMETER C_HAS_IVR = 0
 BUS_INTERFACE SDCR = dcr_v29_0
 PORT DCR_Clk = sys_clk_s
 PORT DCR_Rst = sys_bus_reset
END

BEGIN opb_pci_ref
 PARAMETER INSTANCE = opb_pci_ref_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0x20000000
 PARAMETER C_HIGHADDR = 0x3fffffff
 BUS_INTERFACE MSOPB = opb
 PORT PCLK_IN = PCI_CLK
 PORT REQ_N = PCI_REQ_N
 PORT RST_N = PCI_RST_N
 PORT ACK64_N = PCI_ACK64_N
 PORT AD = PCI_AD
 PORT CBE = PCI_CBE
 PORT DEVSEL_N = PCI_DEVSEL_N
 PORT FRAME_N = PCI_FRAME_N
 PORT IDSEL = PCI_IDSEL
 PORT IRDY_N = PCI_IRDY_N
 PORT PAR = PCI_PAR
 PORT PERR_N = PCI_PERR_N
 PORT REQ64_N = PCI_REQ64_N
 PORT SERR_N = PCI_SERR_N
 PORT STOP_N = PCI_STOP_N
 PORT TRDY_N = PCI_TRDY_N
 PORT FRAMEQ_N = PCI_FRAMEQ_N
 PORT IRDYQ_N = PCI_IRDYQ_N
 PORT GRST_N = PCI_GRST_N
 PORT INTR_OUT = PCI_INTR_OUT
 PORT INTA = PCI_INTA
 PORT INTB = PCI_INTB
 PORT INTC = PCI_INTC
 PORT INTD = PCI_INTD
END

BEGIN opb_tsd_ref
 PARAMETER INSTANCE = opb_tsd_ref_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xaa000000
 PARAMETER C_HIGHADDR = 0xaa000007
 BUS_INTERFACE SOPB = opb
 PORT Intr = TSD_intr
 PORT DCLK = TSD_CLK
 PORT DIN = TSD_DIN
 PORT CS = TSD_CS
 PORT DOUT = TSD_DOUT
 PORT BUSY = TSD_BUSY
 PORT PENIRQ = TSD_PENIRQ
END

BEGIN dcr_v29
 PARAMETER INSTANCE = dcr_v29_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_USE_LUT_OR = 0
END
----------------------------------------------------------------------------------------------------------------------------------------------------------------
PARAMETER


BUS CONNECTIONS





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Observer
Observer
13,052 Views
Registered: ‎10-04-2007

Reference design for touch screen

--------------------------------------------------------------------------------------

Overview


This module is an On-Chip Peripheral Bus (OPB) slave device that is designed to control a
touch screen digitizer chip. It is designed to interface to the Texas Instruments (Burr-Brown) ADS7846 touch screen controller chip present on the ML300 board but will likely work with other compatible digitizer chips. The OPB Touch Screen Controller module utilizes the Xilinx Intellectual Property InterFace (IPIF) to simplify its design. Interrupts for “pen-down“ and “pen-up“ events are also supported.

        Related Documents


The following documents provide additional information:


• IPIF Specification
• IBM CoreConnect™ 64-Bit On-Chip Peripheral Bus: Architecture Specifications, Version 2.1
• Virtex-II Pro™ Platform FPGAs (Data Sheets)
Texas Instruments (Burr-Brown) ADS7846 Touch Screen Controller Data Sheet

Features


• 32-bit OPB slave utilizing a 32-bit IPIF Slave SRAM interface
• Handles serial-to-parallel and parallel-to-serial data conversions
• Generates interrupts for “pen-down” and “pen-up” events


----------------------------------------------------------------------------------------------------------------------------------------------------------------

After I read it . I think that "  need OPB_IPIF for touch screen " . But i don't know " that is right or wrong???" Hope you can help me >thank you

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Xilinx Employee
Xilinx Employee
13,030 Views
Registered: ‎08-06-2007

Hi,
 
It looks like the PowerPC don't have any way of reading/writing to the touchscreen peripheral.
The plb2opb bridge will bridge over all PLB accesses in the adress range of the RNG0 (defined for the bridge).
You have set the range to 0x4000_0000 to 0x7FFF_FFFF.
 
But on the touchscreen peripheral, you have set it's address range to 0xAA00_0000.
 
There is no way for the PowerPC to access those register since the adresses will NOT pass the bridge.
 
You also seems to have the wrong adress for other opb peripherals like opb_pci and the opb2dcr.
 
You need to either reassign the addresses or widen the address range that crosses the plb2opb bridge.
 
The error message from XPS actually gives you hints about this since it writes:
 
WARNING:MDT - Peripheral opb_tsd_ref_0 is not connected to any of the processors


in the system. Check for the following reasons.


1. opb_tsd_ref_0 is not connected to any of the buses connected to a


processor.


2. opb_tsd_ref_0 does not have adresses set correctly.


3. opb_tsd_ref_0's address is not within any of the bridge windows connected


to a processor.


 
The point 3 was exactly the problem here.
 
Göran Bilski


Message Edited by goran_bilski on 10-31-2007 10:41 AM
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Observer
Observer
13,024 Views
Registered: ‎10-04-2007

thank your reply , i will fix them .
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Observer
Observer
13,013 Views
Registered: ‎10-04-2007

Thank you again , I solve that problem , I continue to finished my project . If I have some problem that i can't solve . Hope you can continue helping me .thank you
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Observer
Observer
13,012 Views
Registered: ‎10-04-2007

Help me please , opb_uart 16550 , i can't use it .Help me.



Both of file "touchscreen_int.c" and "touchscreen_polled.c" have " #include "xuartns550_l.h" " . I found them on xilinx.com . But when i use opb_uart 16550 .........





APPEAR ERRORS :
-------------------------------------------------------------------------------------
INFO:coreutil - Valid license for feature opb_uart16550_v1_00_c not found.
You may use the customization GUI for this core but you will
not be able to generate any implementation or simulation files.
Contact Xilinx to obtain a full license for this LogiCORE. For more
information please refer to www.xilinx.com/ipcenter/ipevaluation/
FLEXlm Error: No such feature exists (-5,21)
ERROR:MDT - opb_uart16550 (opb_uart16550_0) - C:\thanh\system.mhs:360 - invalid
license or no license found!
plb_v34 (plb) - C:\thanh\system.mhs:101 - 2 master(s) : 3 slave(s)
opb_v20 (opb) - C:\thanh\system.mhs:111 - 1 master(s) : 8 slave(s)
dcr_v29 (dcr_v29_0) - C:\thanh\system.mhs:354 - 1 master(s) : 2 slave(s)
ERROR:MDT - Errors occured while creating Hardware System
make: *** [ppc405_0/lib/libxil.a] Error 2

Done.
----------------------------------------------------------------------------------------------------------------------------------------------------------------------

I visit xilinx.com but my request was denied because i don't have Product ID number .So please you help me .Thank you

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Explorer
Explorer
12,973 Views
Registered: ‎09-16-2007

Update your tool or goto IP catalog click on Communications Low-SPEED then add the OPB UART (LITE)  and your done
Cheers,
Bill Tomb
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