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Visitor
Visitor
5,979 Views
Registered: ‎03-08-2010

lwIP applications in xapp1026

     Hello everyone, I am now learning the lwIP following the directions in xapp1026, my FPGA is Spartan 3E starter kit and the version of SDK is 11.4.

     I have already created a hardware platform and a standalone software platform and the echo server application works fine in my hardware platform, however, when I try to implement the other applications mentioned in xapp1026, I am engaged in troubles. I've already modified the mss file to fit into Spartan 3e so that the sock_platform is now successfully built, however, when running the sock_apps , I have the following output:

-----lwIP Socket Mode Demo Application ------ Board IP: 128.128.0.138 Netmask : 140.140.0.140 Gateway : 152.152.152.153 Server Port Connect With.. -------------------- ------ -------------------- echo server 7 $ telnet <board_ip> 7 rxperf server 5001 $ iperf -c <board ip> -i 5 -t 100 txperf client N/A $ iperf -s -i 5 -t 100 (on host with IP 192.168.1.10 0) tftp server 69 $ tftp -i 192.168.1.10 PUT <source-file> http server 80 Point your web browser to http://192.168.1.10 Connecting to iperf server...error in connect

 I can still use "ping 192.168.1.10" to check the connection between PC and the FPGA, however the echo server won't  echo any more. Web server replies nothing and tftp get results in time out, can anyone help me ? Following is my mss file and mhs file, thanks!

 

sock_platform.mss

PARAMETER VERSION = 2.2.0 BEGIN OS PARAMETER OS_NAME = xilkernel PARAMETER OS_VER = 4.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER STDIN = RS232_DCE PARAMETER STDOUT = RS232_DCE PARAMETER SYSTMR_SPEC = TRUE PARAMETER SYSTMR_DEV = xps_timer_0 PARAMETER SYSINTC_SPEC = xps_intc_0 PARAMETER enhanced_features = true PARAMETER config_yield = true PARAMETER config_sema = true PARAMETER max_sem_waitq = 20 PARAMETER max_sem = 50 PARAMETER config_time = true PARAMETER max_tmrs = 20 PARAMETER max_readyq = 20 PARAMETER max_pthread_mutex = 20 PARAMETER pthread_stack_size = 32768 PARAMETER systmr_freq = 50000000 PARAMETER static_pthread_table = ((main_thread,1)) END BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu PARAMETER DRIVER_VER = 1.12.b PARAMETER HW_INSTANCE = microblaze_0 PARAMETER COMPILER = mb-gcc PARAMETER ARCHIVER = mb-ar END BEGIN DRIVER PARAMETER DRIVER_NAME = mpmc PARAMETER DRIVER_VER = 3.01.a PARAMETER HW_INSTANCE = DDR_SDRAM END BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.13.a PARAMETER HW_INSTANCE = DIP_Switches_4Bit END BEGIN DRIVER PARAMETER DRIVER_NAME = emaclite PARAMETER DRIVER_VER = 2.01.a PARAMETER HW_INSTANCE = Ethernet_MAC END BEGIN DRIVER PARAMETER DRIVER_NAME = gpio PARAMETER DRIVER_VER = 2.13.a PARAMETER HW_INSTANCE = LEDs_8Bit END BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.14.a PARAMETER HW_INSTANCE = RS232_DCE END BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = dlmb_cntlr END BEGIN DRIVER PARAMETER DRIVER_NAME = bram PARAMETER DRIVER_VER = 1.00.a PARAMETER HW_INSTANCE = ilmb_cntlr END BEGIN DRIVER PARAMETER DRIVER_NAME = uartlite PARAMETER DRIVER_VER = 1.14.a PARAMETER HW_INSTANCE = mdm_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = intc PARAMETER DRIVER_VER = 1.11.a PARAMETER HW_INSTANCE = xps_intc_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = tmrctr PARAMETER DRIVER_VER = 1.11.a PARAMETER HW_INSTANCE = xps_timer_0 END BEGIN LIBRARY PARAMETER LIBRARY_NAME = xilmfs PARAMETER LIBRARY_VER = 1.00.a PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER numbytes = 2000000 PARAMETER base_address = 0x45000000 PARAMETER init_type = MFSINIT_IMAGE PARAMETER need_utils = true END BEGIN LIBRARY PARAMETER LIBRARY_NAME = lwip130 PARAMETER LIBRARY_VER = 1.00.b PARAMETER PROC_INSTANCE = microblaze_0 PARAMETER api_mode = SOCKET_API PARAMETER tcp_wnd = 4096 END

 and my system.mhs is

 

PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX_pin, DIR = I PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX_pin, DIR = O PORT fpga_0_LEDs_8Bit_GPIO_IO_O_pin = fpga_0_LEDs_8Bit_GPIO_IO_O_pin, DIR = O, VEC = [0:7] PORT fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin, DIR = I, VEC = [0:3] PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR = O PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR = O, VEC = [1:0] PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR = O, VEC = [12:0] PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR = IO, VEC = [15:0] PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR = O, VEC = [1:0] PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR = IO, VEC = [1:0] PORT fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin, DIR = IO PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0] PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0] PORT fpga_0_Ethernet_MAC_PHY_MDC_pin = fpga_0_Ethernet_MAC_PHY_MDC_pin, DIR = O PORT fpga_0_Ethernet_MAC_PHY_MDIO_pin = fpga_0_Ethernet_MAC_PHY_MDIO_pin, DIR = IO PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1 BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER C_AREA_OPTIMIZED = 1 PARAMETER C_INTERCONNECT = 1 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_ICACHE_BASEADDR = 0x44000000 PARAMETER C_ICACHE_HIGHADDR = 0x47ffffff PARAMETER C_CACHE_BYTE_SIZE = 2048 PARAMETER C_ICACHE_ALWAYS_USED = 1 PARAMETER C_DCACHE_BASEADDR = 0x44000000 PARAMETER C_DCACHE_HIGHADDR = 0x47ffffff PARAMETER C_DCACHE_BYTE_SIZE = 2048 PARAMETER C_DCACHE_ALWAYS_USED = 1 PARAMETER HW_VER = 7.20.d PARAMETER C_USE_ICACHE = 1 PARAMETER C_USE_DCACHE = 1 BUS_INTERFACE DLMB = dlmb BUS_INTERFACE ILMB = ilmb BUS_INTERFACE DPLB = mb_plb BUS_INTERFACE IPLB = mb_plb BUS_INTERFACE DXCL = microblaze_0_DXCL BUS_INTERFACE IXCL = microblaze_0_IXCL BUS_INTERFACE DEBUG = microblaze_0_mdm_bus PORT MB_RESET = mb_reset PORT INTERRUPT = microblaze_0_Interrupt END BEGIN plb_v46 PARAMETER INSTANCE = mb_plb PARAMETER HW_VER = 1.04.a PORT PLB_Clk = clk_50_0000MHz PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = ilmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = clk_50_0000MHz PORT SYS_Rst = sys_bus_reset END BEGIN lmb_v10 PARAMETER INSTANCE = dlmb PARAMETER HW_VER = 1.00.a PORT LMB_Clk = clk_50_0000MHz PORT SYS_Rst = sys_bus_reset END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr PARAMETER HW_VER = 2.10.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = dlmb BUS_INTERFACE BRAM_PORT = dlmb_port END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = ilmb_cntlr PARAMETER HW_VER = 2.10.b PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00001fff BUS_INTERFACE SLMB = ilmb BUS_INTERFACE BRAM_PORT = ilmb_port END BEGIN bram_block PARAMETER INSTANCE = lmb_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = ilmb_port BUS_INTERFACE PORTB = dlmb_port END BEGIN xps_uartlite PARAMETER INSTANCE = RS232_DCE PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 0 PARAMETER HW_VER = 1.01.a PARAMETER C_BASEADDR = 0x84000000 PARAMETER C_HIGHADDR = 0x8400ffff BUS_INTERFACE SPLB = mb_plb PORT RX = fpga_0_RS232_DCE_RX_pin PORT TX = fpga_0_RS232_DCE_TX_pin END BEGIN xps_gpio PARAMETER INSTANCE = LEDs_8Bit PARAMETER C_ALL_INPUTS = 0 PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_INTERRUPT_PRESENT = 0 PARAMETER C_IS_DUAL = 0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81400000 PARAMETER C_HIGHADDR = 0x8140ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_IO_O_pin END BEGIN xps_gpio PARAMETER INSTANCE = DIP_Switches_4Bit PARAMETER C_ALL_INPUTS = 1 PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_INTERRUPT_PRESENT = 0 PARAMETER C_IS_DUAL = 0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81420000 PARAMETER C_HIGHADDR = 0x8142ffff BUS_INTERFACE SPLB = mb_plb PORT GPIO_IO_I = fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin END BEGIN mpmc PARAMETER INSTANCE = DDR_SDRAM PARAMETER C_NUM_PORTS = 1 PARAMETER C_SPECIAL_BOARD = S3E_STKIT PARAMETER C_MEM_TYPE = DDR PARAMETER C_MEM_PARTNO = MT46V32M16-6 PARAMETER C_MEM_BANKADDR_WIDTH = 2 PARAMETER C_MEM_DATA_WIDTH = 16 PARAMETER C_MEM_DM_WIDTH = 2 PARAMETER C_MEM_DQS_WIDTH = 2 PARAMETER C_PIM0_BASETYPE = 1 PARAMETER C_XCL0_B_IN_USE = 1 PARAMETER HW_VER = 5.04.a PARAMETER C_MPMC_BASEADDR = 0x44000000 PARAMETER C_MPMC_HIGHADDR = 0x47ffffff BUS_INTERFACE XCL0 = microblaze_0_IXCL BUS_INTERFACE XCL0_B = microblaze_0_DXCL PORT MPMC_Clk0 = clk_100_0000MHzDCM0 PORT MPMC_Clk90 = clk_100_0000MHz90DCM0 PORT MPMC_Rst = sys_periph_reset PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin END BEGIN xps_ethernetlite PARAMETER INSTANCE = Ethernet_MAC PARAMETER HW_VER = 3.01.a PARAMETER C_BASEADDR = 0x81000000 PARAMETER C_HIGHADDR = 0x8100ffff PARAMETER C_RX_PING_PONG = 1 PARAMETER C_TX_PING_PONG = 1 BUS_INTERFACE SPLB = mb_plb PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin PORT PHY_MDC = fpga_0_Ethernet_MAC_PHY_MDC_pin PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt PORT PHY_MDIO = fpga_0_Ethernet_MAC_PHY_MDIO_pin END BEGIN xps_timer PARAMETER INSTANCE = xps_timer_0 PARAMETER C_COUNT_WIDTH = 32 PARAMETER C_ONE_TIMER_ONLY = 0 PARAMETER HW_VER = 1.01.b PARAMETER C_BASEADDR = 0x83c00000 PARAMETER C_HIGHADDR = 0x83c0ffff BUS_INTERFACE SPLB = mb_plb PORT Interrupt = xps_timer_0_Interrupt END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKIN_FREQ = 50000000 PARAMETER C_CLKOUT0_FREQ = 100000000 PARAMETER C_CLKOUT0_PHASE = 90 PARAMETER C_CLKOUT0_GROUP = DCM0 PARAMETER C_CLKOUT0_BUF = TRUE PARAMETER C_CLKOUT1_FREQ = 100000000 PARAMETER C_CLKOUT1_PHASE = 0 PARAMETER C_CLKOUT1_GROUP = DCM0 PARAMETER C_CLKOUT1_BUF = TRUE PARAMETER C_CLKOUT2_FREQ = 50000000 PARAMETER C_CLKOUT2_PHASE = 0 PARAMETER C_CLKOUT2_GROUP = NONE PARAMETER C_CLKOUT2_BUF = TRUE PARAMETER HW_VER = 3.02.a PORT CLKIN = dcm_clk_s PORT CLKOUT0 = clk_100_0000MHz90DCM0 PORT CLKOUT1 = clk_100_0000MHzDCM0 PORT CLKOUT2 = clk_50_0000MHz PORT RST = net_gnd PORT LOCKED = Dcm_all_locked END BEGIN mdm PARAMETER INSTANCE = mdm_0 PARAMETER C_MB_DBG_PORTS = 1 PARAMETER C_USE_UART = 1 PARAMETER C_UART_WIDTH = 8 PARAMETER HW_VER = 1.00.g PARAMETER C_BASEADDR = 0x84400000 PARAMETER C_HIGHADDR = 0x8440ffff BUS_INTERFACE SPLB = mb_plb BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus PORT Debug_SYS_Rst = Debug_SYS_Rst END BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER HW_VER = 2.00.a PORT Slowest_sync_clk = clk_50_0000MHz PORT Ext_Reset_In = sys_rst_s PORT MB_Debug_Sys_Rst = Debug_SYS_Rst PORT Dcm_locked = Dcm_all_locked PORT MB_Reset = mb_reset PORT Bus_Struct_Reset = sys_bus_reset PORT Peripheral_Reset = sys_periph_reset END BEGIN xps_intc PARAMETER INSTANCE = xps_intc_0 PARAMETER HW_VER = 2.00.a PARAMETER C_BASEADDR = 0x81800000 PARAMETER C_HIGHADDR = 0x8180ffff BUS_INTERFACE SPLB = mb_plb PORT Intr = xps_timer_0_Interrupt&Ethernet_MAC_IP2INTC_Irpt PORT Irq = microblaze_0_Interrupt END

 

 Thanks!

 

 

 

 

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5 Replies
Xilinx Employee
Xilinx Employee
5,962 Views
Registered: ‎01-18-2008

Since ping works, your hardware is working fine. One optimization I'd do is to add barrel shifter to MicroBlaze. It should give a good performance boost.

 

But to as to why TCP isn't working, I'd check the following areas:

 

 - make sure timer interrupts are generated properly. Set a breakpoint at the timer interrupt handler and confirm that the breakpoint is hit periodically.

 - make sure that MSS settings for xilkernel match what is there in the appnote. From a quick glance, I think you do, but just confirm it.

 - Finally, enable the DEBUG parameters in lwIP and get some TCP/IP debugging output. That should give you a good idea of what might be going wrong. 

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Visitor
Visitor
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Registered: ‎03-08-2010

Hi, vsiva, thanks for your reply and I'll check following your suggestions, but my first problem is , how to add barrel shifter to MicroBlaze? I just do not have any sense about it. Thanks!
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

Double click on MicroBlaze in System Assembly View within XPS GUI and check the box.

 

-Felix

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5,115 Views
Registered: ‎11-26-2010

Hi,

 

I have same issue that is reported here. I am implementing the design  described on xapp1026 on SP605. When I implement just RX, TX tests using Iperf minus other services evereything works. But when I try the example that xilinx provides for ISE 12.1 which bundles webserver, TFTP, TX/RX test, Echo server, then I get following message:

-----lwIP Socket Mode Demo Application ------
Board IP: 192.168.1.10
Netmask : 255.255.255.0
Gateway : 192.168.1.1

              Server   Port Connect With..
-------------------- ------ --------------------
         echo server      7 $ telnet <board_ip> 7
       rxperf server   5001 $ iperf -c <board ip> -i 5 -t 100
       txperf client    N/A $ iperf -s -i 5 -t 100 (on host with IP 192.168.1.10
0)
         tftp server     69 $ tftp -i 192.168.1.10 PUT <source-file>
         http server     80 Point your web browser to http://192.168.1.10

Connecting to iperf server...error in connect.

 

 

I have tried pinging the board when teh failure occurs and the board responds and I can see LED blink. I have tried other steps outlined by xapp1026 and vsiva to debug this but to no avail. Has anyone been able to find the root cause of this issue? I see lot of threads mentioning the same issue, but haven't seen a single resolution posted. Here are the files for SP605,  I ported to ISE 12.3: http://www.xilinx.com/support/answers/36054.htm 

 

Thanks for the help,

SD.

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Registered: ‎12-21-2010

I found out a couple of things in pursuing this same issue.

 

1) iperf -c <whatever> fakes you out.  It will merrily send and you aren't really connected.  Switch it around, i.e. use the server mode and that will tell the truth.

2) I haven't gotten xkern to work - but I DID manage to get standalone to work.  The trick here was that the order of enabling interrupts was messed up in platform.c.  The platform.c would enable both Timer and Ethernet, then in the timer setup just enable the Timer, i.e. clearing the Ethernet.  So the trick is to enable both Timer and Ethernet ONCE after everything is setup. This allowed me to run raw-mode reliably!

 

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