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Visitor
Visitor
10,985 Views
Registered: ‎10-25-2007

marvell 88e1111 PHY register reading

Hi,
I am using ML403 board which has Marvell 88e1111 PHY. I am using TEMAC core. When I read PHY register to know the line rate, etc..I see that I am not geeting correct  value. I tried by setting PHY address to 0x0 and 0x1. But no change. When I read the line rate it shows '11'(binay) which is invalid state. Am I reading with correct address? What else might be the problem? Please comment.
 
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Explorer
Explorer
10,959 Views
Registered: ‎09-16-2007

try phy #7 not sure but thats what the 405 is
 
also make sure you are calling it correctly
 
#include "mdio.h"
extern XTemacIf_Config XTemacIf_ConfigTable[];
 
 
inside main()
int main(void)
{
    XTemacIf_Config *xtemacif_ptr = &XTemacIf_ConfigTable[0];
    XTemac mac = *(xtemacif_ptr->instance_ptr);  
    XStatus status = XST_SUCCESS;
   
    // enabling cache for the microkernel
    XCache_EnableICache( 1 );
    XCache_EnableDCache( 1 );  
 
    status = ReadAllRegMDIO( &mac );
    if( status == XST_FAILURE )
    {
        if( DEBUG_LEVEL >= CRITICAL )
        {
            xil_printf( "ReadAllRegMDIO failed, terminating application\r\n" );
        }
       
        return XST_FAILURE;
    }
 
-----MDIO .c file do this
#include "mdio.h"
XStatus ReadAllRegMDIO( XTemac *mac )
{
    int i;
    Xuint32 PHYADDR;
    Xuint32 Mdio_Reg;
    Xuint16 Register;
    XStatus status;
    PHYADDR = 2;
  //status = XTemac_Initialize( mac, XPAR_PLB_TEMAC_0_DEVICE_ID); you may need this
  //  XTemac_PhySetMdioDivisor(&TemacInstance, 16); //53
    for (i=0; i<32; i++)
    {
        status = XTemac_PhyRead( mac, PHYADDR, i, &Register );
        if( status != XST_SUCCESS )
        {
            if( DEBUG_LEVEL >= CRITICAL )
            {
                xil_printf("ERROR: Unable to read reg %d\r\n", i );
            }
            return XST_FAILURE;
        }
        else
        {
            if( DEBUG_LEVEL == DEBUG )
            {
                xil_printf("PHY addr 0x%x  reg %d  is : 0x%04x\r\n", PHYADDR, i, Register);
            }
        }
    }
}
Cheers,
Bill Tomb
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Explorer
Explorer
10,943 Views
Registered: ‎08-14-2007

Other sources of the problem can be that the PHY is being not released from reset, or that the MDC clock is not being generated properly. For the EMAC core's, it generates the clock signal via a divisor based upon the system input clock to the EMAC core. You may want to ensure that the divisor is set properly based upon the system clock you're using for the EMAC.
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