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Explorer
Explorer
9,687 Views
Registered: ‎04-07-2013

none of awid,no awid, wid, bid and arid in AXI port

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I met a problem on AXI4 interface.
I export an AXI port of Microblaze Interconnect Block. Then Generate Block Design.
I want to connect PCIe AXI4 signals to Microblaze on the top level. But I found that there is no awid, wid, bid and arid signals output by Microblaze Interconnect AXI Master.
Usually, I connect the AXI interface in IP Integrator, then the AXI Master port of Microblaze Interconnect will have thosed id signals.

 

Can anyone give some hints?

 

Thanks!

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Explorer
Explorer
18,027 Views
Registered: ‎04-07-2013

 

You are right.  There is no burst, len, size signals either.  That is AXI LITE!

I let IPI generate an AXI Interconnect IP after adding a Microblaze.  I think it is Data Peripheral.

Seems like the AXI port of AXI Interconnect will become full if we connect it to a full AXI port in IPI and then click Generate Block Design.

 

In this case, I need to package my RTL to IP core and add it in IPI. 

May be that is only way?

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Anonymous
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Lack of ID signals is the biggest different between AXI full and AXI Lite. However I would also expect you to be mismatched on the BURST, CACHE, LEN, LOCK, PROT, QOS and SIZE signals on the AR and AW channels too if that is the case.

IDs are tricky in AXI, as the width of the signal is implementation defined. I wonder if 0 (no signal) is simply valid. So even if you did have ID signals, you would need a pre-existing policy on the ID widths that was consistent accross your connected IPs or have an interconnect sort it out.

Microblaze has two AXI data interfaces, the cached (DC) and the peripheral (DP). I think they are AXI full and AXI lite resp. Which one are you using?

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Explorer
Explorer
18,028 Views
Registered: ‎04-07-2013

 

You are right.  There is no burst, len, size signals either.  That is AXI LITE!

I let IPI generate an AXI Interconnect IP after adding a Microblaze.  I think it is Data Peripheral.

Seems like the AXI port of AXI Interconnect will become full if we connect it to a full AXI port in IPI and then click Generate Block Design.

 

In this case, I need to package my RTL to IP core and add it in IPI. 

May be that is only way?

View solution in original post

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Anonymous
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Hi,

 

If you are doing RTL connection you can just tie off the unused signals. An AXIL master is interoperable with an AXI full slave.

 

It is however a design red flag. Your bandwidth is severly limited in that you have a LITE master in your data-path. If bandwidth is of no concern than you are good though.

 

Document ARM IHI 0022D covers interoperability of AXIL and AXI full and how you can direct connect with the right tie-offs.

 

There is yet another option, and that is to connect to MB via the DC interface rather than DP so it is AXI full. Then your PCIe peripheral will be in MBs cacheable region and you can use cache-lines to implement burst transactions to your PCIe

 

HTH

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