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Visitor
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Registered: ‎03-19-2009

ppc440mc_ddr2 Timing Error

When building the EDK system, I’ve tried to use both the given ppc440mc_ddr2 UCF for the V5 FX30T devices (-2 stepping), and a UCF generated from MIG and ported over to EDK. The EDK project is an un-modified system generated directly from base system builder. I’ve relaxed the appropriate UCF constraints for the DDR2 controller to function at 300 MHz, and they are all met without issues. However,  I’m having trouble with one timing constraint that isn’t defined in the UCF. Between the sys_clk (100 MHz) and the PPC440 CPMMCCLK90 (200 MHz), there is a constraint between the rising edges at 1.25 ns. It looks like this in the timing report:

 

Timing constraint: TS_clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4__0 =

PERIOD TIMEGRP         "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4__0"

TS_sys_clk_pin         / 2 PHASE 1.25 ns HIGH 50%;

 

 898 paths analyzed, 764 endpoints analyzed, 272 failing endpoints

 272 timing errors detected. (272 setup errors, 0 hold errors)

 Minimum period is   9.848ns.

--------------------------------------------------------------------------------

Slack:                  -1.212ns (requirement - (data path - clock path skew + uncertainty))

  Source:               DDR2_SDRAM_W1D32M72R8A_5A/DDR2_SDRAM_W1D32M72R8A_5A/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel (FF)

  Destination:          DDR2_SDRAM_W1D32M72R8A_5A/DDR2_SDRAM_W1D32M72R8A_5A/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_30 (FF)

  Requirement:          1.250ns

  Data Path Delay:      2.026ns (Levels of Logic = 1)

  Clock Path Skew:      -0.229ns (2.768 - 2.997)

  Source Clock:         sys_clk_s rising at 0.000ns

  Destination Clock:    ppc440_0_CPMMCCLK90 rising at 1.250ns

  Clock Uncertainty:    0.207ns

 

Do you have an ideas as to why a default system, with the default UCF, has this error?

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