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Observer wen119at
Observer
8,532 Views
Registered: ‎02-16-2010

problem about create and import peripheral~help~~~~~~~~~~

Hello everyone
I am using EDK11.4 and i am making a project on xilinx EDK XPS. im using the Create and Import Peripheral to create my own ip. then im integrating an independent vhdl file with it. it is basically a multiplier. my vhdl file has two 16 bit input ports and one 32 bit outputs. i want to send data to my ip from the C application software written in the xps project but i am unable to do so. The idea is to somehow connect my ip ports FIFO (chosen when creating the new ip template), then write/read data to/from the WFIFO and RFIFO. The ports of the ip will be declared in the user_logic.vhd and a port map is written in the user_logic.vhd as well. The actual multiplication will be performed in the vhdl file-newip.vhd. I am unable to get the right results. Can anyone help me to figure out what is the problem… Thanks in advance.
My declaration in user_logic.vhd is:

The step I followed is:

1.    Create and Import peripheral-> create a new ip template (choose Read/Write FIFO only, no s/w accessible registers)

Address Block Summary:

user logic slv : C_BASEADDR + 0x00000000: C_BASEADDR + 0x000000FFrdfifo reg : C_BASEADDR + 0x00000100: C_BASEADDR + 0x000001FFrdfifo data : C_BASEADDR + 0x00000200: C_BASEADDR + 0x000002FFwrfifo reg : C_BASEADDR + 0x00000300: C_BASEADDR + 0x000003FFwrfifo data : C_BASEADDR + 0x00000400: C_BASEADDR + 0x000004FF

 

2.    Open a new file in XPS and write newip.vhd file for my created IP. Save this file in the same folder with user_logic.vhd file which is generated automatically when creating the IP in XPS.

Source code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity newip is   

Port ( clk : in  STD_LOGIC;          

a : in  STD_LOGIC_VECTOR (15 downto 0);          

b : in  STD_LOGIC_VECTOR (15 downto 0);          

p : out  STD_LOGIC_VECTOR (31 downto 0));

end newip; 

architecture Behavioral of newip is 

begin 

process (clk) 

begin   

if (clk'event and clk = '1') then     

p <= unsigned(a) * unsigned(b);   

end if;

end process;  

end Behavioral;

3.    Make changes to user_logic.vhd file:

a.    Component declaration:

--USER signal declarations added here, as needed for user logic  

component newip   

Port ( clk : in  STD_LOGIC;          

a : in  STD_LOGIC_VECTOR (15 downto 0);          

b : in  STD_LOGIC_VECTOR (15 downto 0);          

p : out  STD_LOGIC_VECTOR (31 downto 0));  

end component;

b.    Port map:

--USER logic implementation added here  

uut_newip: newip   

port map (   

clk => Bus2IP_Clk,   

a => WFIFO2IP_Data(16 to 31),   

b => WFIFO2IP_Data(0 to 15),

p => IP2RFIFO_Data);

 

4.    Make changes to PAO file:

lib my_ip_v1_00_a newip vhdl

lib my_ip_v1_00_a user_logic vhdl

lib my_ip_v1_00_a my_ip vhdl

5. Since there is no other ports, so I leave both MPD file and top level (my_ip.vhd) default.

 

6.    Import this peripheral using PAO file.

7.    Double click the IP and add it to the embedded system.

8.    Make connection to mb_plb bus.

9.    Allocate address for this IP.

10. Launch SDK and write the following source code:

 

#include "xparameters.h"

#include "xbasic_types.h"

#include "xstatus.h"

#include "my_ip.h"

#include "xuartns550_l.h" 

Xuint32 *baseaddr_p = (Xuint32 *)XPAR_MY_IP_0_BASEADDR; 

int main (void) {  Xuint32 i;  Xuint32 temp;  Xuint32 baseaddr;

 /* Setup 16550 Uart */   

XUartNs550_SetBaud( XPAR_UARTNS550_0_BASEADDR, XPAR_CPU_CORE_CLOCK_FREQ_HZ, 9600);    

XUartNs550_mSetLineControlReg(XPAR_UARTNS550_0_BASEADDR, XUN_LCR_8_DATA_BITS); 

// Clear the screen  xil_printf("%c[2J",27);   

// Check that the peripheral exists  //XASSERT_NONVOID(baseaddr_p != XNULL); 

baseaddr = (Xuint32) baseaddr_p;   

xil_printf("Multiplier Test\n\r");  

// Reset read and write packet FIFOs to initial state 

MY_IP_mResetWriteFIFO(baseaddr); 

MY_IP_mResetReadFIFO(baseaddr);  

// Push data to write packet FIFO 

for(i = 1; i <= 4; i++ ){    

 temp = (i << 16) + i;   

xil_printf("Wrote: 0x%08x \n\r",temp);   

MY_IP_mWriteToFIFO(baseaddr, MY_IP_WRFIFO_DATA_SPACE_OFFSET, temp);  

}  

// pop data out from read packet FIFO 

for(i = 0; i < 4; i++){  

temp = MY_IP_mReadFromFIFO(baseaddr, MY_IP_RDFIFO_DATA_SPACE_OFFSET);  

xil_printf("Read:  0x%08x \n\r",temp); 

}  

// Reset the read and write FIFOs 

MY_IP_mResetWriteFIFO(baseaddr);  

MY_IP_mResetReadFIFO(baseaddr);  

xil_printf("End of test\n\n\r");

}

 The output in HyperTerminal is: 

Multiplier Test

Wrote: 0x00010001

Wrote: 0x00020002

Wrote: 0x00030003

Wrote: 0x00040004

Read:  0x00000000

Read:  0x00000000

Read:  0x00000000

Read:  0x00000000

End of test 

 

I have no idea about this problem. I am a starter to EDK, can anyone help me out?How can I check out whether the data has been written to WRFIFO?Thanks in advance.(I find there are some one saying that changed should be made to BBD file, I have no idea about this and I don’t know when it is needed to change this file. Do I need to change this file in my design?) 

Message Edited by wen119at on 03-05-2010 08:24 AM
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8 Replies
Scholar pumaju1808
Scholar
8,513 Views
Registered: ‎08-14-2007

Re: problem about create and import peripheral~help~~~~~~~~~~

Hi wen,

 

do you add your library in the user_logic.vhd code??

 

you should put this in your user_logic file in order to use your newip instance:

 

--USER libraries added here
library my_ip_v1_00_a;
use my_ip_v1_00_a.all;

 

then you instance your newip like this:

 

--USER logic implementation added here  

uut_newip:entity my_ip_v1_00_a.newip   

port map (   

clk => Bus2IP_Clk,   

a => WFIFO2IP_Data(16 to 31),   

b => WFIFO2IP_Data(0 to 15),

p => IP2RFIFO_Data);

 

 Another thing important is that when you made this changes and when you import your peripheral make sure that when wizard ask you for your vhdl sources, you must include your newip.vhd file, this makes changes in your PAO file automatically

 

If this is not working i suggest that first test without using newip.vhd file, you make the multiplication directly in your user_logic file, then see what happens

 

Regards

 

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Scholar pumaju1808
Scholar
8,512 Views
Registered: ‎08-14-2007

Re: problem about create and import peripheral~help~~~~~~~~~~

Also when you add Read/Write FIFO servicesin your custom IP,the wizard automatically add a "test code" for your fifo in the user_logic file, i don't remember if you have to request Read and Write access to your fifo, maybe you have to. Check the test code to see how write and read from/to FIFO

 

regards

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Xilinx Employee
Xilinx Employee
8,489 Views
Registered: ‎08-07-2007

Re: problem about create and import peripheral~help~~~~~~~~~~

Hi,

 

Are you sure you want to define "baseaddr_p" as a pointer in your C code? 

 

You are assigning the content of the pointer "baseaddr_p" to baseaddr, not the address "XPAR_MY_IP_0_BASEADDR".

 

-Felix

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Observer wen119at
Observer
8,465 Views
Registered: ‎02-16-2010

Re: problem about create and import peripheral~help~~~~~~~~~~

Hi pumaju,

 

Thanks very much for your reply. Got it done~:)

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Observer wen119at
Observer
8,464 Views
Registered: ‎02-16-2010

Re: problem about create and import peripheral~help~~~~~~~~~~

Hi,

 

I thought that "Xuint32 *baseaddr_p = (Xuint32 *)XPAR_MY_IP_0_BASEADDR; " will assign XPAR_MY_IP_0_BASEADDR to baseaddr_p... Isn't the case? I am really puzzled about this...Do you think i should use: baseaddr = XPAR_MY_IP_0_BASEADDR instead?

 

winnie

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Adventurer
Adventurer
6,631 Views
Registered: ‎10-23-2010

Re: problem about create and import peripheral~help~~~~~~~~~~

 hi all


how you are correct this problem wen119at

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Moderator
Moderator
6,626 Views
Registered: ‎11-10-2010

Re: problem about create and import peripheral~help~~~~~~~~~~

gemna,

wen119at mentioned pumaju1808's suggestion had solved the issue. Have you tried their suggestions?
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Adventurer
Adventurer
6,623 Views
Registered: ‎10-23-2010

Re: problem about create and import peripheral~help~~~~~~~~~~

Hi 

In message 1 pumaju has proposed to add library to user logic .

I don't think that it's the right solution. I think that the second one is the right solution .

 

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