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Contributor
Contributor
6,527 Views
Registered: ‎03-31-2010

problem with FIFO ? help

i create and import an ip workin as pwm generator. i like to the put the value of my duty cycle from software so i add a FIFO with ip and i modify the fsm. i attached the project if someone can find the error or the problem because i write the c program like this :

#include "xparameters.h"
#include "xbasic_types.h"
#include "xstatus.h"
#include "pwm_ip2.h"
    Xuint32 baseaddr = 0x7bc00000 ;
    #define temp 0x0000000a

int main (void) {

    PWM_IP2_mResetWriteFIFO (baseaddr);
    PWM_IP2_mResetReadFIFO  (baseaddr);

    xil_printf("Wrote: 0x%08x \n\r", 10);
    PWM_IP2_mWriteToFIFO(baseaddr, temp);
}

but the value was not filled to right variable N and no output is generated

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8 Replies
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Contributor
Contributor
6,523 Views
Registered: ‎03-31-2010

i well be grateful and specially very happy if someone help or give a way to write data to an ip from th software.

N.B : i work with MBlaze and the board is spartan3

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Xilinx Employee
Xilinx Employee
6,512 Views
Registered: ‎02-25-2009

I have the following observations from your files:-

 

 

 

1) You are writing into WFIFO from sw code, so you need to generate read request for WFIFO from state machine written in user_logic.vhd.

 

 

 

2) You need to check whether WFIFO is empty. If it is not empty (WFIFO2IP_empty = '0')

 

then generate read request (IP2WFIFO_RdReq) and upon getting read ack from WFIFO (WFIFO2IP_RdAck = '1') go back to original state.

3) Try to map with 24 to 31 bits of WFIFO, like,

N =>WFIFO2IP_Data(24 to 31),

 

I think if you can simulate the design using Modelsim SE/PE, it will give you better idea.

Thanks,

 

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Contributor
Contributor
6,493 Views
Registered: ‎03-31-2010

thx for the answer. but if you can explain the two first point in other word. and just a remark the same processes if i implement them in the user_logic and i fix the N i obtain an output and if i fix the N and i add the third vhdl file (pwm_bloc) that describe the pwm fonction the ip does not generate the output.??why i dont know.
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Contributor
Contributor
6,457 Views
Registered: ‎03-31-2010

please some help. i am lost and i need to slove this problem.

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Contributor
Contributor
6,384 Views
Registered: ‎03-31-2010

hi,

really i need help. there is no one who can check the attached file and give a solution or how to communicate with the  ip ?

any help

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Contributor
Contributor
6,367 Views
Registered: ‎03-26-2009

hello, 

 

Sorry, I don't have the solution, just some questions to try to help:

 

Have you read the IP datasheet?

 

Where do you expect to see the signal  N?

 

How does the validation signal work? I don't understand the pwm logic, the N =>WFIFO2IP_Data(0 to 7) is registered internally?

 

good luck,

 

 

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Xilinx Employee
Xilinx Employee
6,329 Views
Registered: ‎08-06-2007

Hi,

 

Have you tried to simulate?

It's usually the best way to debug an issue.

 

Göran

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Contributor
Contributor
6,300 Views
Registered: ‎03-31-2010

thx for the help.

i found the error it was int fsm of FIFO the data pass from write to read fifo very fast and the ip bloc dont get the data .

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