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mars9050
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Registered: ‎05-12-2008

problems using two hard ethernet macs on V5 with XPS (unconstrained LOC for IDELAYCTRL)

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Hi,

 

I'm trying to use two ethernet macs on a virtex5 LX110T. Currently, I'm using Xilinx Platform Studio 9.2i and the XPS_LL_TEMAC ip version 1.00b to interface to the two hard ethernet MACs on the fpga.

 

The problem I'm encountering is that tools complain about unconstrained LOC on IDELAYCTRL elements. Apparently, the IP does not provide a LOC constraint, and the tools can handle at most one unconstrained IDELAYCTRL.

 

Per the Xilinx answer record on this topic, I've tried to provide a LOC constraint based on some random guesses as to a workable location. My guesses so far have resulted in unroutable nets and failed timing. Can someone tell me how I might determine a suitible location for the IDELAYCTRL element for the Xilinx IP (short of trying every single IDELAYCTRL element)? I've already tried to look at the output of the place and route using floorplanner on a system that has a single MAC, but I wasn't able to select the IDELAYCTRL and zoom in as with other elements. I suspect that something tricky is going on and the IDELAYCTRL is different from other elements somehow.

 

Thanks,

 

Jeff

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mars9050
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Registered: ‎05-12-2008

I ended up going with centaur19's second suggestion (slightly modified), with success. I LOCed both of the IDELAYCTRL elements provided by the TEMAC pcores, and instantiated two more IDELAYCTRLs using a custom pcore created using the wizard.  After providing LOC constraints for these four IDELAYCTRLs, and filling in some missing clock information in the second TEMAC pcore from the BSB wizard, everything seems to work fine.

 

Thanks again.

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centaur19
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Registered: ‎08-01-2007

Hi mars9050,

 

Which phy interface are you using? 

 

There are 2 ways of dealing with IDELAYCTRLs:

 

1. You instantiate and LOC them as required.

2. Alternatively, you can instantiate a single IDELAYCTRL and not LOC it. That way the tools will replicate them as required.

 

The issue with the 9.2i core was that the number of instantiated IDELAYCTRLs were fixed and they were LOCed. In the case of two MACs, it would be 2, which is probably not enough, depending on your pin-out. The best way to determine the location will be to look at the placement of the RX signals (RXC and RXD) and use the IDELAYCTRL in that bank.

 

To address this issue, there are a couple of workarounds.

 

1. Upgrade to 10.1i. This issue has been fixed and you will have to LOC the required number.

2. If you want to continue with 9.2i, you may want to create a pcore which instantiates just a single IDELAYCTRL and let the tools take care of the placement. Additionally, the placement of the instantiated IDELAYCTRLs will probably not be right and hence you may require additional directives in the UCF.

 

For example,

INST "Hard_Ethernet_MAC/*?dlyctrl0" LOC = "IDELAYCTRL_X1Y4";

 

where "Hard_Ethernet_MAC" is the instance name of XPS_LL_TEMAC.

 

Hope this helps.....

 

 

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mars9050
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Hi centaur19.

 

 I'm using the avnet virtex5lx110t pcie development board, which comes with National DP83865DVH 10/100/1000 phys. Upgrading to 10.1 is not a simple proposition for me as avnet refuses to support this (brand new) board with anything other than 9.2, and the board definition files they provide for 9.2 do not work with 10.1.

 

 I'll open up the floorplanner to figure out which IDELAYCTRLs are in the io banks with the receive pins, do a test that LOCs the IDELAYCTRLs to a location in the recieve pin banks, and report the results.

 

Thanks for your help,

 

Jeff

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mars9050
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Registered: ‎05-12-2008

I ended up going with centaur19's second suggestion (slightly modified), with success. I LOCed both of the IDELAYCTRL elements provided by the TEMAC pcores, and instantiated two more IDELAYCTRLs using a custom pcore created using the wizard.  After providing LOC constraints for these four IDELAYCTRLs, and filling in some missing clock information in the second TEMAC pcore from the BSB wizard, everything seems to work fine.

 

Thanks again.

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