04-14-2008 01:06 AM - edited 04-14-2008 11:59 PM
#
# Display IP and peripheral ports
#
# do jtagppc_0_wave.do
# do xps_bram_if_cntlr_1_wave.do
# do plb_bram_if_cntlr_1_bram_wave.do
do RS232_Uart_wave.do
# do Push_Buttons_Position_wave.do
# do SRAM_wave.do
# do ppc405_0_iocm_cntlr_wave.do
# do isocm_bram_wave.do
# do ppc405_0_docm_cntlr_wave.do
# do dsocm_bram_wave.do
# do SRAM_util_bus_split_0_wave.do
# do clock_generator_0_wave.do
# do proc_sys_reset_0_wave.do
do test_ip_0_wave.do
I tried cleaning simulation, then regenerate Simulation HDL Files, modified the system_wave.do file. After several clicking the "Launch HDL Simulator", the following is the output:
At Local date and time: Mon Apr 14 16:01:12 2008
xbash -q -c "cd /cygdrive/c/IWC_Projects/Module1/; /usr/bin/make -f system.make
simmodel; exit;" started...
Done!
At Local date and time: Mon Apr 14 16:01:24 2008
xbash -q -c "cd /cygdrive/c/IWC_Projects/Module1/; /usr/bin/make -f system.make
simmodel; exit;" started...
Done!
At Local date and time: Mon Apr 14 16:01:12 2008
xbash -q -c "cd /cygdrive/c/IWC_Projects/Module1/; /usr/bin/make -f system.make
simmodel; exit;" started...
Done!
At Local date and time: Mon Apr 14 16:01:24 2008
xbash -q -c "cd /cygdrive/c/IWC_Projects/Module1/; /usr/bin/make -f system.make
simmodel; exit;" started...
Done!
WITHOUT displaying MODELSIM!!!
Can anyone tell me how to fix this???
04-15-2008 02:32 PM
04-15-2008 06:17 PM
04-15-2008 07:01 PM - edited 04-15-2008 07:15 PM
Compiling opb_monitor_bfm_v1_00_a
Executing: vlib C:/ISE_EDK_Lib/EDK_Lib/opb_monitor_bfm_v1_00_a
Executing: vmap opb_monitor_bfm_v1_00_a C:/ISE_EDK_Lib/EDK_Lib/opb_monitor_bfm_v1_00_a
Modifying C:\ISE_EDK_Lib\EDK_Lib\modelsim.ini
Executing: vcom -93 -novopt -quiet -work opb_monitor_bfm_v1_00_a -f C:/ISE_EDK_Lib/EDK_Lib/CompileListFiles/opb_monitor_bfm_v1_00_a_compile_order
** Error: C:/Xilinx/10.1/EDK/hw/XilinxBFMinterface/pcores/opb_monitor_bfm_v1_00_a/hdl/vhdl/opb_monitor_bfm.vhd(261): (vcom-1272) Length of formal "opb_mxgrant" is 3; length of actual is 16.
** Error: C:/Xilinx/10.1/EDK/hw/XilinxBFMinterface/pcores/opb_monitor_bfm_v1_00_a/hdl/vhdl/opb_monitor_bfm.vhd(296): VHDL Compiler exiting
ERROR:: Failed to execute vcom -93 -novopt -quiet -work opb_monitor_bfm_v1_00_a -f C:/ISE_EDK_Lib/EDK_Lib/CompileListFiles/opb_monitor_bfm_v1_00_a_compile_order :
modelsim>do system_setup.doNext, I compiled, resulting into an error.
# Setting up simulation commands ...
# **********************************************************************
# **********************************************************************
# ***
# *** Simulation Setup Macros (system_setup.do)
# ***
# *** c => compile the design by running the EDK compile script.
# *** Assumes ISE and EDK libraries were compiled earlier
# *** for ModelSim. (see system.do)
# ***
# *** m => modify the modelsim.ini file to use SmartModels.
# *** Use this command after compiling the design with
# *** the 'c' command and before using the 's' command.
# ***
# *** s => load the design for simulation. (ModelSim 'vsim'
# *** command with 'system_tb') After loading the design,
# *** set up signal displays (optional) and run the simulation.
# *** (ModelSim 'run' command)
# ***
# *** l => set up signal list display and launch a list window.
# *** ModelSim 'add -list' commands are found in *_list.do
# *** scripts. (see system_list.do)
# ***
# *** w => set up signal wave display and launch a waveform window.
# *** ModelSim 'add -wave' commands are found in *_wave.do
# *** scripts. (see system_wave.do)
# ***
# *** h => print this message
# ***
# **********************************************************************
# **********************************************************************
modelsim>cI observed that there is one modelsim.ini in the edk folder that is rewritable, the one that is in the modeltech directory is not.
# ** Error: (vmap-20) Cannot access for writing file "c:\Modeltech_eval_6.3c\modelsim.ini".
# Permission denied. (errno = EACCES)
# Error in macro ./system.do line 7
# ** Error: (vmap-20) Cannot access for writing file "c:\Modeltech_eval_6.3c\modelsim.ini".
# Permission denied. (errno = EACCES)
# while executing
# "vmap XilinxCoreLib "C:/ISE_EDK_Lib/ISE_Lib/XilinxCoreLib/""
# 1
04-15-2008 07:07 PM - edited 04-15-2008 07:14 PM
PATH = C:\Modeltech_eval_6.3c\win32;C:\Modeltech_eval_6.3c\win32peI checked, and the executable ModelSim is found on the win32pe folder.
MODELSIM = c:\Modeltech_eval_6.3c\modelsim.ini
04-17-2008 11:08 AM
04-25-2008 12:29 AM
04-25-2008 12:32 AM
04-25-2008 02:57 PM
Chris,
Have you tried setting all the environment variables listed above?
04-28-2008 12:17 AM
Yes, I think so...
What I did are the following:
On desktop:
right-click on "My Computer" -> "Properties" -> "Advanced" -> Button "Environment Variables"
In the top Window named "User Variables" I added two Variables, it then kind of looks like:
Variable | Value
______________________
MODELSIM C:\Modeltech_6.3c\modelsim.ini
PATH C:\Modeltech_6.3c\win32
(there are couple of other Variables, too, they've been there before)
I guess that is what you are referring to? If not, which file do I have to edit to get it run?
Thanks
Chris
04-28-2008 02:04 AM
Okay. I somehow got it...
I added the MODELSIM Variable today, (MODELSIM C:\Modeltech_6.3c\modelsim.ini, my last post) and now, after finally rebooting my computer, it works.
But it works only once per session. After clicking on "launch hdl simulator" Modelsim opens for the first time and I am able to simulate. After closing Modelsim, I tried to simulate again, but nothing happens. Even when I close the Project and open it again or opening another Project it won't help, Modelsim just doesn't start. Only after closing the whole XPS and open it again, I am able to load modelsim again, and again only for one time.
That's strange, isn't it? Do you have any suggestions on how I can fix this?
Thanks
Chris