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Registered: ‎07-21-2008

sysgen core reading error using FSL bus


hello Iam using vertex2pro kit  and using sysgen for genetaion of the pcores .Iam using fsl bus every thing .I followed in what it is their in your excersise .I also marked the register readback option also but Iam unable to read the values from register output .I took a simple DAfir filter and made all constants one and passing inputs to DaFIR my expected output will be 1 2 3 4 5 1  for the input 1 1 1 1 1 1
please hlp me i stucked this problem from 6 months please help me out.I tried with combinational logic it came but sequential how to do that .

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