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Visitor haibo2806
Visitor
1,611 Views
Registered: ‎12-05-2012

the transmit performance of lwip with spartan6 is low

I have a sp605 board, I download the XAPP1026,and i test the performance of Lwip in RAW mode in ISE 13.1, the transmit and receive

performance is about 110Mbit/s and 120Mbit/s.
But if I creat a new sdk project with ISE 13.1 or ISE 13.2,the transmit thoughout is about 110Mbit/s and the receive thoughout is

only 60Mbit/s.
The strange thing is that when I  creat a new sdk project with ISE 13.4,the transmit thoughout is as low as as 50Mbit/s but the

receive thoughout is about 120Mbit/s.
The same thing apear when I use my own PCB board ,my microblaze paremeter is:
i_cache:32k
d_cache:16k

When I use the lwip with the jumbo frames, the transmit thoughout is about 120Mbit/s and the receive thoughout is about 330Mbit/s.
I doult there is some wrong with the system, I think the transmit performance can rise a lot.

Please help me what the problem with my system.

My system.mhs file is as follwing:


# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd
# Thu Nov 29 20:56:09 2012
# Target Board:  xilinx.com sp605 Rev C
# Family:    spartan6
# Device:    xc6slx45t
# Package:   fgg484
# Speed Grade:  -3
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT zio = zio, DIR = IO
 PORT rzq = rzq, DIR = IO
 PORT mcbx_dram_we_n = mcbx_dram_we_n, DIR = O
 PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n, DIR = IO
 PORT mcbx_dram_udqs = mcbx_dram_udqs, DIR = IO
 PORT mcbx_dram_udm = mcbx_dram_udm, DIR = O
 PORT mcbx_dram_ras_n = mcbx_dram_ras_n, DIR = O
 PORT mcbx_dram_odt = mcbx_dram_odt, DIR = O
 PORT mcbx_dram_ldm = mcbx_dram_ldm, DIR = O
 PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n, DIR = IO
 PORT mcbx_dram_dqs = mcbx_dram_dqs, DIR = IO
 PORT mcbx_dram_dq = mcbx_dram_dq, DIR = IO, VEC = [15:0]
 PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst, DIR = O
 PORT mcbx_dram_clk_n = mcbx_dram_clk_n, DIR = O, SIGIS = CLK
 PORT mcbx_dram_clk = mcbx_dram_clk, DIR = O, SIGIS = CLK
 PORT mcbx_dram_cke = mcbx_dram_cke, DIR = O
 PORT mcbx_dram_cas_n = mcbx_dram_cas_n, DIR = O
 PORT mcbx_dram_ba = mcbx_dram_ba, DIR = O, VEC = [2:0]
 PORT mcbx_dram_addr = mcbx_dram_addr, DIR = O, VEC = [12:0]
 PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O
 PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I
 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT Push_Buttons_4Bits_TRI_I = Push_Buttons_4Bits_TRI_I, DIR = I, VEC = [3:0]
 PORT Linear_Flash_we_n = Linear_Flash_we_n, DIR = O
 PORT Linear_Flash_reset = Linear_Flash_reset, DIR = O
 PORT Linear_Flash_oe_n = Linear_Flash_oe_n, DIR = O
 PORT Linear_Flash_data = Linear_Flash_data, DIR = IO, VEC = [0:15]
 PORT Linear_Flash_ce_n = Linear_Flash_ce_n, DIR = O
 PORT Linear_Flash_adv_n = Linear_Flash_adv_n, DIR = O
 PORT Linear_Flash_address = Linear_Flash_address, DIR = O, VEC = [0:23]
 PORT LEDs_4Bits_TRI_O = LEDs_4Bits_TRI_O, DIR = O, VEC = [3:0]
 PORT ETHERNET_TX_ER = ETHERNET_TX_ER, DIR = O
 PORT ETHERNET_TX_EN = ETHERNET_TX_EN, DIR = O
 PORT ETHERNET_TX_CLK = ETHERNET_TX_CLK, DIR = O
 PORT ETHERNET_TXD = ETHERNET_TXD, DIR = O, VEC = [7:0]
 PORT ETHERNET_RX_ER = ETHERNET_RX_ER, DIR = I
 PORT ETHERNET_RX_DV = ETHERNET_RX_DV, DIR = I
 PORT ETHERNET_RX_CLK = ETHERNET_RX_CLK, DIR = I
 PORT ETHERNET_RXD = ETHERNET_RXD, DIR = I, VEC = [7:0]
 PORT ETHERNET_PHY_RST_N = ETHERNET_PHY_RST_N, DIR = O
 PORT ETHERNET_MII_TX_CLK = ETHERNET_MII_TX_CLK, DIR = I
 PORT ETHERNET_MDIO = ETHERNET_MDIO, DIR = IO
 PORT ETHERNET_MDC = ETHERNET_MDC, DIR = O
 PORT DIP_Switches_4Bits_TRI_I = DIP_Switches_4Bits_TRI_I, DIR = I, VEC = [3:0]
 PORT sys_clk_pin = CLK_S, CLK_FREQ = 50000000, DIR = I, SIGIS = CLK


BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Slowest_sync_clk = clk_50_0000MHzPLL0
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN axi_intc
 PARAMETER INSTANCE = microblaze_0_intc
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT IRQ = microblaze_0_interrupt
 PORT S_AXI_ACLK = clk_50_0000MHzPLL0
 PORT INTR = ETHERNET_INTERRUPT & axi_timer_0_Interrupt & ETHERNET_dma_mm2s_introut & ETHERNET_dma_s2mm_introut
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHzPLL0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_100_0000MHzPLL0
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.20.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_USE_FPU = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_ICACHE_BASEADDR = 0xa8000000
 PARAMETER C_ICACHE_HIGHADDR = 0xafffffff
 PARAMETER C_USE_ICACHE = 1
 PARAMETER C_CACHE_BYTE_SIZE = 32768
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BASEADDR = 0xa8000000
 PARAMETER C_DCACHE_HIGHADDR = 0xafffffff
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 16384
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER C_USE_HW_MUL = 1
 PARAMETER C_USE_DIV = 0
 PARAMETER C_ICACHE_STREAMS = 0
 PARAMETER C_ICACHE_VICTIMS = 8
 PARAMETER C_DCACHE_USE_WRITEBACK = 0
 PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_B_REGISTER = 1
 BUS_INTERFACE M_AXI_DP = axi4lite_0
 BUS_INTERFACE M_AXI_IP = axi4lite_0
 BUS_INTERFACE M_AXI_DC = axi4_0
 BUS_INTERFACE M_AXI_IC = axi4_0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_100_0000MHzPLL0
 PORT INTERRUPT = microblaze_0_interrupt
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_USE_UART = 1
 PARAMETER C_BASEADDR = 0x41400000
 PARAMETER C_HIGHADDR = 0x4140ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_50_0000MHzPLL0
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 600000000
 PARAMETER C_CLKOUT0_GROUP = PLL0
 PARAMETER C_CLKOUT0_BUF = FALSE
 PARAMETER C_CLKOUT1_FREQ = 600000000
 PARAMETER C_CLKOUT1_PHASE = 180
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT1_BUF = FALSE
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_GROUP = PLL0
 PARAMETER C_CLKOUT3_FREQ = 125000000
 PARAMETER C_CLKOUT3_GROUP = NONE
 PARAMETER C_CLKOUT4_FREQ = 133333333
 PARAMETER C_CLKOUT4_GROUP = NONE
 PARAMETER C_CLKOUT0_DUTY_CYCLE = 0.500000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT1_DUTY_CYCLE = 0.500000
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT2_DUTY_CYCLE = 0.500000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT3_DUTY_CYCLE = 0.500000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT4_BUF = TRUE
 PARAMETER C_CLKOUT4_DUTY_CYCLE = 0.5
 PARAMETER C_CLKOUT4_PHASE = 0
 PARAMETER C_CLKOUT5_BUF = TRUE
 PARAMETER C_CLKOUT5_DUTY_CYCLE = 0.500000
 PARAMETER C_CLKOUT5_FREQ = 50000000
 PARAMETER C_CLKOUT5_GROUP = PLL0
 PARAMETER C_CLKOUT5_PHASE = 0
 PORT LOCKED = proc_sys_reset_0_Dcm_locked
 PORT CLKOUT2 = clk_100_0000MHzPLL0
 PORT RST = RESET
 PORT CLKOUT0 = clk_600_0000MHzPLL0_nobuf
 PORT CLKOUT1 = clk_600_0000MHz180PLL0_nobuf
 PORT CLKOUT4 = clk_133_3333MHz
 PORT CLKOUT3 = clk_125_0000MHz
 PORT CLKIN = CLK_S
 PORT CLKOUT5 = clk_50_0000MHzPLL0
END

BEGIN axi_timer
 PARAMETER INSTANCE = axi_timer_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_COUNT_WIDTH = 32
 PARAMETER C_ONE_TIMER_ONLY = 0
 PARAMETER C_BASEADDR = 0x41c00000
 PARAMETER C_HIGHADDR = 0x41c0ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT S_AXI_ACLK = clk_50_0000MHzPLL0
 PORT Interrupt = axi_timer_0_Interrupt
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4lite_0
 PARAMETER HW_VER = 1.05.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
 PORT INTERCONNECT_ACLK = clk_50_0000MHzPLL0
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi4_0
 PARAMETER HW_VER = 1.05.a
 PORT interconnect_aclk = clk_100_0000MHzPLL0
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 1
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT TX = RS232_Uart_1_sout
 PORT RX = RS232_Uart_1_sin
 PORT S_AXI_ACLK = clk_50_0000MHzPLL0
END

BEGIN axi_gpio
 PARAMETER INSTANCE = Push_Buttons_4Bits
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT GPIO_IO_I = Push_Buttons_4Bits_TRI_I
 PORT S_AXI_ACLK = clk_50_0000MHzPLL0
END

BEGIN axi_s6_ddrx
 PARAMETER INSTANCE = MCB_DDR3
 PARAMETER HW_VER = 1.05.a
 PARAMETER C_MCB_RZQ_LOC = K7
 PARAMETER C_MCB_ZIO_LOC = M7
 PARAMETER C_MEM_TYPE = DDR3
 PARAMETER C_MEM_PARTNO = MT41J64M16XX-187E
 PARAMETER C_MEM_BANKADDR_WIDTH = 3
 PARAMETER C_MEM_NUM_COL_BITS = 10
 PARAMETER C_SKIP_IN_TERM_CAL = 0
 PARAMETER C_S0_AXI_ENABLE = 1
 PARAMETER C_INTERCONNECT_S0_AXI_MASTERS = microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC & ETHERNET_dma.M_AXI_SG &

ETHERNET_dma.M_AXI_MM2S & ETHERNET_dma.M_AXI_S2MM
 PARAMETER C_INTERCONNECT_S0_AXI_AW_REGISTER = 8
 PARAMETER C_INTERCONNECT_S0_AXI_AR_REGISTER = 8
 PARAMETER C_INTERCONNECT_S0_AXI_W_REGISTER = 8
 PARAMETER C_INTERCONNECT_S0_AXI_R_REGISTER = 8
 PARAMETER C_INTERCONNECT_S0_AXI_B_REGISTER = 8
 PARAMETER C_S0_AXI_BASEADDR = 0xa8000000
 PARAMETER C_S0_AXI_HIGHADDR = 0xafffffff
 BUS_INTERFACE S0_AXI = axi4_0
 PORT zio = zio
 PORT rzq = rzq
 PORT s0_axi_aclk = clk_100_0000MHzPLL0
 PORT ui_clk = clk_100_0000MHzPLL0
 PORT mcbx_dram_we_n = mcbx_dram_we_n
 PORT mcbx_dram_udqs_n = mcbx_dram_udqs_n
 PORT mcbx_dram_udqs = mcbx_dram_udqs
 PORT mcbx_dram_udm = mcbx_dram_udm
 PORT mcbx_dram_ras_n = mcbx_dram_ras_n
 PORT mcbx_dram_odt = mcbx_dram_odt
 PORT mcbx_dram_ldm = mcbx_dram_ldm
 PORT mcbx_dram_dqs_n = mcbx_dram_dqs_n
 PORT mcbx_dram_dqs = mcbx_dram_dqs
 PORT mcbx_dram_dq = mcbx_dram_dq
 PORT mcbx_dram_ddr3_rst = mcbx_dram_ddr3_rst
 PORT mcbx_dram_clk_n = mcbx_dram_clk_n
 PORT mcbx_dram_clk = mcbx_dram_clk
 PORT mcbx_dram_cke = mcbx_dram_cke
 PORT mcbx_dram_cas_n = mcbx_dram_cas_n
 PORT mcbx_dram_ba = mcbx_dram_ba
 PORT mcbx_dram_addr = mcbx_dram_addr
 PORT sysclk_2x = clk_600_0000MHzPLL0_nobuf
 PORT sysclk_2x_180 = clk_600_0000MHz180PLL0_nobuf
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT PLL_LOCK = proc_sys_reset_0_Dcm_locked
END

BEGIN axi_emc
 PARAMETER INSTANCE = Linear_Flash
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_TYPE = 2
 PARAMETER C_TCEDV_PS_MEM_0 = 130000
 PARAMETER C_TAVDV_PS_MEM_0 = 130000
 PARAMETER C_THZCE_PS_MEM_0 = 35000
 PARAMETER C_TWC_PS_MEM_0 = 70000
 PARAMETER C_TWP_PS_MEM_0 = 70000
 PARAMETER C_TLZWE_PS_MEM_0 = 35000
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_S_AXI_MEM0_BASEADDR = 0x42000000
 PARAMETER C_S_AXI_MEM0_HIGHADDR = 0x43ffffff
 BUS_INTERFACE S_AXI_MEM = axi4lite_0
 PORT Mem_WEN = Linear_Flash_we_n
 PORT Mem_RPN = Linear_Flash_reset
 PORT Mem_OEN = Linear_Flash_oe_n
 PORT Mem_DQ = Linear_Flash_data
 PORT Mem_CEN = Linear_Flash_ce_n
 PORT Mem_ADV_LDN = Linear_Flash_adv_n
 PORT Mem_A = 0b0000000 & Linear_Flash_address & 0b0
 PORT S_AXI_ACLK = clk_50_0000MHzPLL0
 PORT RdClk = clk_50_0000MHzPLL0
END

BEGIN axi_gpio
 PARAMETER INSTANCE = LEDs_4Bits
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT GPIO_IO_O = LEDs_4Bits_TRI_O
 PORT S_AXI_ACLK = clk_50_0000MHzPLL0
END

BEGIN axi_dma
 PARAMETER INSTANCE = ETHERNET_dma
 PARAMETER HW_VER = 5.00.a
 PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1
 PARAMETER C_SG_USE_STSAPP_LENGTH = 1
 PARAMETER C_INCLUDE_MM2S_DRE = 1
 PARAMETER C_INCLUDE_S2MM_DRE = 1
 PARAMETER C_DLYTMR_RESOLUTION = 1250
 PARAMETER C_PRMRY_IS_ACLK_ASYNC = 0
 PARAMETER C_SG_INCLUDE_STSCNTRL_STRM = 1
 PARAMETER C_SG_LENGTH_WIDTH = 16
 PARAMETER C_INCLUDE_MM2S = 1
 PARAMETER C_INCLUDE_S2MM = 1
 PARAMETER C_BASEADDR = 0x41e00000
 PARAMETER C_HIGHADDR = 0x41e0ffff
 PARAMETER C_MM2S_BURST_SIZE = 256
 PARAMETER C_S2MM_BURST_SIZE = 256
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_WRITE_FIFO_DEPTH = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_READ_FIFO_DEPTH = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_WRITE_FIFO_DEPTH = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_READ_FIFO_DEPTH = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_WRITE_FIFO_DEPTH = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_READ_FIFO_DEPTH = 0
 BUS_INTERFACE S_AXI_LITE = axi4lite_0
 BUS_INTERFACE M_AXI_SG = axi4_0
 BUS_INTERFACE M_AXI_MM2S = axi4_0
 BUS_INTERFACE M_AXI_S2MM = axi4_0
 BUS_INTERFACE M_AXIS_MM2S = ETHERNET_dma_txd
 BUS_INTERFACE M_AXIS_MM2S_CNTRL = ETHERNET_dma_txc
 BUS_INTERFACE S_AXIS_S2MM_STS = ETHERNET_dma_rxs
 BUS_INTERFACE S_AXIS_S2MM = ETHERNET_dma_rxd
 PORT s_axi_lite_aclk = clk_100_0000MHzPLL0
 PORT m_axi_sg_aclk = clk_100_0000MHzPLL0
 PORT m_axi_mm2s_aclk = clk_100_0000MHzPLL0
 PORT m_axi_s2mm_aclk = clk_100_0000MHzPLL0
 PORT mm2s_prmry_reset_out_n = AXI_STR_TXD_ARESETN
 PORT mm2s_cntrl_reset_out_n = AXI_STR_TXC_ARESETN
 PORT s2mm_prmry_reset_out_n = AXI_STR_RXD_ARESETN
 PORT s2mm_sts_reset_out_n = AXI_STR_RXS_ARESETN
 PORT mm2s_introut = ETHERNET_dma_mm2s_introut
 PORT s2mm_introut = ETHERNET_dma_s2mm_introut
END

BEGIN axi_ethernet
 PARAMETER INSTANCE = ETHERNET
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_PHYADDR = 0B00001
 PARAMETER C_INCLUDE_IO = 1
 PARAMETER C_TYPE = 1
 PARAMETER C_PHY_TYPE = 1
 PARAMETER C_HALFDUP = 0
 PARAMETER C_TXMEM = 16384
 PARAMETER C_RXMEM = 16384
 PARAMETER C_TXCSUM = 2
 PARAMETER C_RXCSUM = 2
 PARAMETER C_TXVLAN_TRAN = 0
 PARAMETER C_RXVLAN_TRAN = 0
 PARAMETER C_TXVLAN_TAG = 0
 PARAMETER C_RXVLAN_TAG = 0
 PARAMETER C_TXVLAN_STRP = 0
 PARAMETER C_RXVLAN_STRP = 0
 PARAMETER C_MCAST_EXTEND = 0
 PARAMETER C_STATS = 0
 PARAMETER C_AVB = 0
 PARAMETER C_INTERCONNECT_S_AXI_IS_ACLK_ASYNC = 0
 PARAMETER C_BASEADDR = 0x40c40000
 PARAMETER C_HIGHADDR = 0x40c7ffff
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi4lite_0
 BUS_INTERFACE AXI_STR_TXD = ETHERNET_dma_txd
 BUS_INTERFACE AXI_STR_TXC = ETHERNET_dma_txc
 BUS_INTERFACE AXI_STR_RXS = ETHERNET_dma_rxs
 BUS_INTERFACE AXI_STR_RXD = ETHERNET_dma_rxd
 PORT REF_CLK = clk_133_3333MHz
 PORT GTX_CLK = clk_125_0000MHz
 PORT GMII_TX_ER = ETHERNET_TX_ER
 PORT GMII_TX_EN = ETHERNET_TX_EN
 PORT GMII_TX_CLK = ETHERNET_TX_CLK
 PORT GMII_TXD = ETHERNET_TXD
 PORT GMII_RX_ER = ETHERNET_RX_ER
 PORT GMII_RX_DV = ETHERNET_RX_DV
 PORT GMII_RX_CLK = ETHERNET_RX_CLK
 PORT GMII_RXD = ETHERNET_RXD
 PORT PHY_RST_N = ETHERNET_PHY_RST_N
 PORT MII_TX_CLK = ETHERNET_MII_TX_CLK
 PORT MDIO = ETHERNET_MDIO
 PORT MDC = ETHERNET_MDC
 PORT S_AXI_ACLK = clk_50_0000MHzPLL0
 PORT AXI_STR_TXD_ACLK = clk_100_0000MHzPLL0
 PORT AXI_STR_TXC_ACLK = clk_100_0000MHzPLL0
 PORT AXI_STR_RXD_ACLK = clk_100_0000MHzPLL0
 PORT AXI_STR_RXS_ACLK = clk_100_0000MHzPLL0
 PORT AXI_STR_TXD_ARESETN = AXI_STR_TXD_ARESETN
 PORT AXI_STR_TXC_ARESETN = AXI_STR_TXC_ARESETN
 PORT AXI_STR_RXD_ARESETN = AXI_STR_RXD_ARESETN
 PORT AXI_STR_RXS_ARESETN = AXI_STR_RXS_ARESETN
 PORT INTERRUPT = ETHERNET_INTERRUPT
END

BEGIN axi_gpio
 PARAMETER INSTANCE = DIP_Switches_4Bits
 PARAMETER HW_VER = 1.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE S_AXI = axi4lite_0
 PORT GPIO_IO_I = DIP_Switches_4Bits_TRI_I
 PORT S_AXI_ACLK = clk_50_0000MHzPLL0
END

 

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