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Explorer
Explorer
5,118 Views
Registered: ‎09-11-2012

timing constraint ignored in planahead 14.3

Hi,

 

I am currently design a system using planahead 14.3. The whole system is transferred from ISE to planahead in netlist format. However, when I add timing constrains as following:

 

# System clock
NET SYSCLK_P TNM_NET = sys_clk;
NET SYSCLK_N TNM_NET = sys_clk_n;
TIMESPEC TS_sys_clk = PERIOD sys_clk 5000 ps HIGH 50%;
TIMESPEC TS_sys_clk_n = PERIOD sys_clk_n 5000 ps HIGH 50%;

 

Planahead gives me a critical warning saying saying that 

  • [Constraints 18-329] No definition for group 'sys_clk', timing constraint is ignored 
  • [Constraints 18-329] No definition for group 'sys_clk_n', timing constraint is ignored 

I have already reading similar discussions online by haven't got a solution. Had anyone encountered similar problem before? Thanks.

 

T

 

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1 Reply
Xilinx Employee
Xilinx Employee
5,097 Views
Registered: ‎06-14-2012

Re: timing constraint ignored in planahead 14.3

Hi

Please open synthesized design and see the exact name for your system clock nets. Then change them accordingly.

Its not picking it properly.

 

If its a differential pair, please check the following article.

http://www.xilinx.com/support/answers/15833.html

 

Hope this helps.

 

Regards

Sikta

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