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Anonymous
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using FSL bus to transfer data in/out of microblaze

Hello All.  I want to see if anyone here can offer some insight to what I'm trying to accomplish.  Thanks for your time.

 

I have an ISE project where I've instantiated a microblaze processor.  That has worked well, and I'm able to generate a hardware interrupt signal from the ISE design into the interrupt controller in the XPS design (passing a pushbutton signal in from a ML506 dev. board to the xps_intc -> interrupt to the microblaze, which prints serial output through a uart).  I'd like a fast way to pass data from the ISE design into the XPS design, so I chose the FSL bus.  This is what I would like to have happen:

 

A VHDL module in ISE will serve as the FSL master. I'll pass the write/clock/data into the XPS design, and the XPS design will provide the FSL full signal to the ISE design.  Can I do it this way, or do I need to have a pcore within XPS work as my peripheral, and then devise a simple way to send the data from ISE to the pcore in XPS?  For now, let's assume I choose to implement a pcore in XPS.

 

These are the applicable portions of my mhs:

 

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 7.10.d
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_FSL_LINKS = 1
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_INSTANCE = microblaze_0
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE SFSL0 = fsl_to_mb0
 BUS_INTERFACE MFSL0 = mb0_to_fsl
 PORT MB_RESET = mb_reset
 PORT INTERRUPT = xps_intc_0_Irq
END

 

Here's the master FSL bus (fsl_to_mb0):

 

BEGIN fsl_v20
 PARAMETER INSTANCE = fsl_to_mb0
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_ASYNC_CLKS = 1
 PARAMETER C_FSL_DWIDTH = 32
 PARAMETER C_USE_CONTROL = 0
# Don't implement in BRAM, use distributed RAM
 PARAMETER C_IMPL_STYLE = 0
 PARAMETER C_FSL_DEPTH = 16
# period in ps of 125MHz clock
 PARAMETER C_READ_CLOCK_PERIOD = 8000
 PORT SYS_Rst = sys_rst_s
 PORT FSL_M_Clk = fsl_to_mb0_FSL_M_Clk
 PORT FSL_S_Clk = sys_clk_s
 PORT FSL_M_Full = fsl_to_mb0_FSL_M_Full
 PORT FSL_M_Write = fsl_to_mb0_FSL_M_Write
 PORT FSL_M_Data = fsl_to_mb0_FSL_M_Data
 PORT FSL_S_Data = fsl_to_mb0_FSL_S_Data
 PORT FSL_S_Read = fsl_to_mb0_FSL_S_Read
 PORT FSL_S_Exists = fsl_to_mb0_FSL_S_Exists
END

 

Here's the slave FSL bus (mb0_to_fsl), in case I need to send data from XPS to ISE:

 

BEGIN fsl_v20
 PARAMETER INSTANCE = mb0_to_fsl
 PARAMETER HW_VER = 2.11.a
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER C_ASYNC_CLKS = 1
 PARAMETER C_FSL_DWIDTH = 32
 PARAMETER C_USE_CONTROL = 0
# Don't implement in BRAM, use distributed RAM
 PARAMETER C_IMPL_STYLE = 0
 PARAMETER C_FSL_DEPTH = 16
# period in ps of 18.75MHz clock
 PARAMETER C_READ_CLOCK_PERIOD = 53333
 PORT SYS_Rst = sys_rst_s
 PORT FSL_M_Clk = sys_clk_s
 PORT FSL_S_Clk = mb0_to_fsl_FSL_S_Clk
 PORT FSL_M_Full = mb0_to_fsl_FSL_M_Full
 PORT FSL_M_Write = mb0_to_fsl_FSL_M_Write
 PORT FSL_M_Data = mb0_to_fsl_FSL_M_Data
 PORT FSL_S_Data = mb0_to_fsl_FSL_S_Data
 PORT FSL_S_Read = mb0_to_fsl_FSL_S_Read
 PORT FSL_S_Exists = mb0_to_fsl_FSL_S_Exists
END

 

Then I have my peripheral defined:

 

BEGIN data_to_mb0
 PARAMETER INSTANCE = data_to_mb0_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE BUS = mb0_to_fsl, BUS_STD = FSL, BUS_TYPE = SLAVE
 PORT FSL_Rst = sys_rst_s
 PORT FSL_S_Clk = sys_clk_s
 PORT FSL_S_Read = FSL_S_Read
 PORT FSL_S_Data = FSL_S_Data
 PORT FSL_S_Exists = FSL_S_Exists
 PORT FSL_M_Clk = FSL_M_Clk
 PORT FSL_M_Write = FSL_M_Write
 PORT FSL_M_Data = FSL_M_Data
 PORT FSL_M_Full = FSL_M_Full
END

 

Right now I'm calling out the signals individually, but I'm not sure that's necessary.  From a top-level block diagram view, this is how I see things connected:

 

Pass data to write, clock, and control signals from ISE to XPS (pcore -> FSL master bus instantiation -> slave fsl microblaze bus interface). 

 

In the other direction: XPS (master fsl microblaze bus interface -> FSL slave bus instantiation -> pcore) to ISE for reading data.

 

Hope this isn't too confusing.

 

I'm trying to follow the FSL pdf manual for specifying the mhs definition in my peripheral.  Copy past from the manual ->

 

BEGIN my_fsl_peripheral

OPTION IPTYPE = PERIPHERAL

OPTION IMP_NETLIST = TRUE

BUS_INTERFACE BUS = FSL_IN, BUS_STD = FSL, BUS_TYPE = SLAVE

BUS_INTERFACE BUS = FSL_OUT, BUS_STD = FSL, BUS_TYPE = MASTER

## Ports

PORT CLK = "", DIR = IN, SIGIS=CLK

PORT RESET = "", DIR = IN

PORT FSL_S_READ = FSL_S_Read, DIR=out, BUS=FSL_IN

PORT FSL_S_DATA = FSL_S_Data, DIR=in, VEC=[0:31], BUS=FSL_IN

PORT FSL_S_CONTROL = FSL_S_Control, DIR=in, BUS=FSL_IN

PORT FSL_S_EXISTS = FSL_S_Exists, DIR=in, BUS=FSL_IN

PORT FSL_M_WRITE = FSL_M_Write, DIR=out, BUS=FSL_OUT

PORT FSL_M_DATA = FSL_M_Data, DIR=out, VEC=[0:31], BUS=FSL_OUT

PORT FSL_M_CONTROL = FSL_M_Control, DIR=out, BUS=FSL_OUT

PORT FSL_M_FULL = FSL_M_Full, DIR=in, BUS=FSL_OUT

END

 

But in doing this, I get the error BUS_INTERFACE BUS not found in mpd.

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Anonymous
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This is kind of messy the way I explained this.  I believe I've found a solution.

 

I don't particularly need the FSL bus implementation (I will control data flow directly in my ISE module and don't need the FIFOs), so I will tie directly into the FSL slave ports on the microblaze (See MB Processor Ref Guide, Table 2-7) through the external ports.  I'm implementing this directly in the mhs file.  One last point of inconsistency:

 

Table 2-7 shows FSL0_S_Clk as an input.  I would think that it should be, as the data is being clocked to the processor by an external peripheral in ISE.  However, the System Assembly View under the Ports tab shows that FSL0_S_Clk is an output.  Perhaps this is just a typo in XPS?  (I'll try to treat it as an input and see if I get synthesis errors.)  If anyone has any info on this, please share.  Thanks.

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