09-27-2012 08:53 PM
Hi,
Has anyone tried to use both cpu cores of zynq?
I did not find any example from Xilinx, only related information
in "Zynq-7000 EPP Technical Reference Manual UG585 (v1.2)".
It says that cpu0 must do these two things:
1. Write the address of the application for CPU1 to 0xFFFFFFF0.
2. Execute the SEV instruction to cause CPU1 to wake up and
jump to the application.
Found a "dual cpu demo" example on ARM web-site:
http://www.arm.com/files/pdf/ZC702_DS5_2.pdf
However, the attached source code doesn't do any of the
above two actions. How can the second cpu start then?
Regards,
Pramod Ranade
03-28-2017 12:13 AM
Hello greatgehar,
thanks for your reply. I think I have already tested this, but i will retry it as far as i can do.
at the moment i got a solution with petalinux on the first core and my app at the secound. this app is using lwip for fast RAW ethernet connection. i tested this standalone bare-metal application for a long time and it works pretty got. in kombination with petalinux on core 0 i have the problem, that i dont receive a "connected callback" from lwip and so i got no connection!
i made a screenshot from the console output:
at the beginning i start the softuart app on cpu0, than i start the core 1 by writing its start adress to 0xFFFFFFF0.
In red is my setup of the scutimer and the phy.
yellow is the connection on port 5001 (for data streaming)
green is a secound tcp connection on port 6001 (for debugging)
at the end i got an ethernet timeout.
could you give me more input what could be wrong?
03-28-2017 01:47 AM
For a long time I have not started the second kernel as you describe.
Now I'm use remoteproc driver for start baremetal on cpu1 and rpmsg for communication between Petalinux on cpu0 and cpu1 (see UG1186). In my system I not use Ethernet from cpu1. All network tasks run on Petalinux and it work fast and fine.
03-28-2017 02:00 AM
04-11-2017 07:24 AM
04-16-2018 02:06 AM
Please have a look here..
https://forums.xilinx.com/t5/OpenAMP/Zynq-AMP-CPU1-baremetal-access-to-gem0/m-p/847163#M470
It should be related to a missing TLB configuration for DDR to make CPU1 works with LwIP..
L