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gsxftxx
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Registered: ‎03-06-2018

using microblaze in virtex 7 to talk to micron parallel nor flash

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Hi there,

 

I have a few doubts about read/write communication between virtex 7 and micron parallel nor flash. 

 

1. Do I need clock output to flash if I just need asynchronous read?

 

2. if I need clock, for virtex 7 I'll need startupe2 ip to provide clock to flash CCLK pin. According to xapp1282, emc and flash should be both working under 50MHz, while microblaze and AXI interconnect should be under 100MHz, as emc is also connected to the AXI interconnect, I got synthesis errors... Anybody has done this??

 

3. If I don't need clock, shall I just do the followings to get the correct query register value?

 

// set flash in asynchronous mode

WRITE_FLASH_16(FLASH_BASE_ADDRESS + 0x17BBE, 0x60606060);
WRITE_FLASH_16(FLASH_BASE_ADDRESS + 0x17BBE, 0x03030303);

// request reading of query register

CfiQryAddr <<= 1; // CfiQryAddr = 0x10
WRITE_FLASH_16(BaseAddress, 0xFF);
WRITE_FLASH_16(BaseAddress + 0xAA, 0x98);
DATA_SYNC;

// read query register
Data16 = READ_FLASH_16(BaseAddress + CfiQryAddr); // Data16 should get value of 0x51

It will be very much appreciated if anybody can give me any hints.

 

 

Elaine

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gsxftxx
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Registered: ‎03-06-2018

@rsclancy Thanks for your help. In the end I used run_xcu108.bat in the source files provided by XAPP1282 to create an Vivado project, then changed my design accordingly, which solved all my problems!

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rsclancy
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Registered: ‎11-25-2013

Elaine,

 

Could you tell us what board you are using ( Xilinx or custom )? if custom could you provide an image of the flash connection to the fpga?

 

In general, yes, you'll need a clock. It depends on how the flash is connected to the FPGA as to whether or not you'll use the STARTUP primitive.

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gsxftxx
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Hi @rsclancy,

 

Thanks for quick reply, I have a custom board, the connections are shown below. As FPGA_CCLK (100 MHz) is provided from XC7VX690T to MT28GU01G, I guess startupe2 is needed. Then I have a further question: according to xapp1282, in order to talk between microblaze and flash, both AXI EMC and Flash is supposed to clocked to 50 MHz, which means in AXI EMC both s_axi_aclk and rdclk should be connected 50 MHz, while microblaze and axi interconnect is clocked at 100 MHz?? Sadly this creates synthesis error. I also attached a block design, please feel free to point out any problem that you've noticed.

 

Many thanks,

Elaine

flash.jpg

bank0.png

other banks.png

munin.png

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rsclancy
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Registered: ‎11-25-2013

Not sure what differs but it looks like you are using a Virtex7 690T part while the XAPP1282 is written for an Ultrascale part.  I'd google to see if there was a BPI flash write up specifically for the Virtex 7. You could also look at the reference design for the VC709 board. The built in standard test (BIST) includes booting from BPI flash. Interestingly they omit the pullup on CCLK in there schematic probably because they are sure to use the internal pullup.

 

If the AXI EMC core must be clocked at 50MHz, then you'll need to generate another clock, preferably from the same core that produces the 100MHz uBlaze clock. 

 

On page 12 of the configuration guide UG470 there is this note:

 

In Master configuration modes, the 7 series device drives CCLK from an internal oscillator. To select the desired frequency, the bitstream -g ConfigRate option is used. The BitGen section of UG628, ISE Command Line Tools User Guide provides more information for the ISE Design Suite. The Device Configuration Bitstream Settings section of UG908, Vivado Programming and Debugging User Guide provides more information for the Vivado Design Suite. After configuration, the CCLK is turned OFF unless the persist option is selected or SEU detection is used. See Persist Option in Chapter 6. The CCLK pin is 3-stated with a weak pull-up.

 

You should have some contraints to get things set right. If you right click on Generate Bitstream you can pull up the Bitstream Setting dialog (once you have an open implemented design). There is a link in the dialog for "Configure additional bitstream settings". You'll want to make sure those settings are correct for you design. The following are from a spi flash example- different- but for reference:

 

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-1 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6C [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]

set_property BITSTREAM.CONFIG.CONFIGRATE 90 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.USERID 32'h59434953 [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

 

 

 

 

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rsclancy
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The XAPP1282 points you in the right direction for your clocking scheme- see image.

 

xapp1282_1.JPG
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gsxftxx
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Registered: ‎03-06-2018

@rsclancy Thanks for your help. In the end I used run_xcu108.bat in the source files provided by XAPP1282 to create an Vivado project, then changed my design accordingly, which solved all my problems!

View solution in original post