UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor aminb
Visitor
2,579 Views
Registered: ‎08-10-2011

using single port rom in EDK

Jump to solution

Hi all

in ise we use CoreGen to add single port rom and specify a coe file as initial data to the created single port rom then we portmap it and use it.

I want to integrate microblaze and VHDL together in xps.

I created a project in xps using bsb.

then I created a custom peripheral to add my VHDL code using this peripheral(by adding my code instance to user logic).

now I want use from a single port rom in my VHDL because I have so many initial data for process. 

can anyone help me plz?

 

 

 

0 Kudos
1 Solution

Accepted Solutions
Explorer
Explorer
3,154 Views
Registered: ‎08-12-2007

Re: using single port rom in EDK

Jump to solution
You can use coregen to generate the ngc core.
When importing your IP to the design with CIP Wizard, select the ngc netlist file. CIP wizard will copy this ngc to pcore/<your IP>/netlists directory and create a bbd file in data directory.

You can refer to psf_rm.pdf in EDK/doc directory for the syntax of BBD file.
0 Kudos
1 Reply
Explorer
Explorer
3,155 Views
Registered: ‎08-12-2007

Re: using single port rom in EDK

Jump to solution
You can use coregen to generate the ngc core.
When importing your IP to the design with CIP Wizard, select the ngc netlist file. CIP wizard will copy this ngc to pcore/<your IP>/netlists directory and create a bbd file in data directory.

You can refer to psf_rm.pdf in EDK/doc directory for the syntax of BBD file.
0 Kudos