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Teacher muzaffer
Teacher
8,259 Views
Registered: ‎03-31-2012

video in to axis 4.0 axis_enable is connected to both clock domains

I am using video in to AXI4 Stream (v4.0) in independent clocking mode and it seems that axis_enable is being used by both clock domains (vid_io_in_clk & aclk) which is causing timing violations regardless to which clock it's synchronized. This seems like a bad design. Any idea how to get around this cleanly?

 

thanks.

 

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Xilinx Employee
Xilinx Employee
8,212 Views
Registered: ‎08-02-2011

Re: video in to axis 4.0 axis_enable is connected to both clock domains

Hmm... I had a quick look at the code and it looks like the new version of the IP indeed seems to use the signal in both domains. Let me look into it.

I've used the new version of the core without issue, but I think I just tied off the axis_enable to vcc.
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Teacher muzaffer
Teacher
8,180 Views
Registered: ‎03-31-2012

Re: video in to axis 4.0 axis_enable is connected to both clock domains

could you please add your experience (new version of the IP indeed seems to use the signal in both domains) to the SR I opened (10340355) on this issue? The datasheet claims that this signal is synchronous to vid_io_in_clk and that's what the person who's handling the case is repeating without looking at the code as you did.

 

Actually when it's fixed I think the axis_enable signal should be synchronous to axi_clk (ie output clock) which is what the name suggests.

 

In the mean time, I changed my code to use the vid_io_in_ce signal which works with a signal synchronous to vid_io_in_clk. I don't see any reason to change this and it's another reason that axis_enable to be synchronous to output clock. I don't see the need to have two enable signals on the same clock domain.

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Xilinx Employee
Xilinx Employee
8,171 Views
Registered: ‎08-02-2011

Re: video in to axis 4.0 axis_enable is connected to both clock domains

I might have spoken too soon. I'm looking into it in more detail.

 

The axis_enable should be synchronous to the input clock domain (despite the nomenclature...). The intent is that it should be driven from the VTC detector's 'locked' bit. This VTC detector instance would be synchronous to the input video's clock domain.

 

The axis_enable signal is essentially a gate to help prevent partial frames come coming through before the VTC locks. Thus, it makes sense that it is in the vid_io_in_clk domain. This is functionally different from the other clock enables for each domain.

 

Do you get timing errors when it's synchronous to the input clock?

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Teacher muzaffer
Teacher
8,169 Views
Registered: ‎03-31-2012

Re: video in to axis 4.0 axis_enable is connected to both clock domains

yes. I get timing errors on the axi clock when it's synchronous to input clock and I get timing errors on vid_io_in_clk domain when it's synchronous to axi clock domain.
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: video in to axis 4.0 axis_enable is connected to both clock domains

Hmmm interesting. I put together a little testcase, but I don't see the path show up in the timing report. Can you show a snippet of your timing report?

Are you using this in IPI? If not, OOC synthesis or no?
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