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Contributor
Contributor
320 Views
Registered: ‎01-11-2018

vivado 2015.4 seems freezed in the routing step when routing the ZC706 PCIE TRD

Hi

I am new to vivado 2015.4 SDK. These days I try to generate bitstream  of ZC706 PCIE TRD. 

But after synthesis step , vivado seems freezed in the routing step. I have tried to wait about 5 hours, it just does not go on . The log print like below.

Any response will make difference! THX ahead.

 

4 Infos, 119 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:08:07 ; elapsed = 00:06:41 . Memory (MB): peak = 2529.328 ; gain = 1.004 ; free physical = 123 ; free virtual = 12472
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:22 ; elapsed = 00:00:11 . Memory (MB): peak = 2529.328 ; gain = 0.000 ; free physical = 125 ; free virtual = 12475
write_checkpoint: Time (s): cpu = 00:00:40 ; elapsed = 00:00:27 . Memory (MB): peak = 2529.328 ; gain = 0.000 ; free physical = 248 ; free virtual = 12473
report_io: Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2529.328 ; gain = 0.000 ; free physical = 248 ; free virtual = 12473
report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2529.328 ; gain = 0.000 ; free physical = 248 ; free virtual = 12473
report_control_sets: Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2529.328 ; gain = 0.000 ; free physical = 247 ; free virtual = 12474
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z045'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z045'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads

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Xilinx Employee
Xilinx Employee
284 Views
Registered: ‎11-05-2019

 

Hello @fujiajun 

 

Is there enough memory, disk space on the your HOST machine?

Is the OS Windows10, Ubuntu16.04?

 

Is it the same when using a simple design only for PS?

If there is no problem with this design, you can narrow it down by trying the PS and PL (only GPiO) designs next time.

 

Thank you


Ka2ki
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Contributor
Contributor
268 Views
Registered: ‎01-11-2018

Thank you for your response.

Just the ZC706 PCIE TRD dont work in vivado 2015.4 , that I have tried vivado 2014.4 or vivado 2017.4 all can get bitstream files.

My host machine runs ubuntu 16.04 and windows 7. On both OS the results are  same .

With  vivado 2015.4 the tools seem fine ,if the project other than the PCIE project, for example I can go through most the example designs of ug1165.

By openning the IO planning of the TRD project I find the PCIE IO are not be located to the pins, should I assign them manually? Or live it be? The TRD project is not be finished, when released?