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8,118 Views
Registered: ‎03-27-2014

vivado & axi lite peripheral: axi_interconnect_synth_failed

Hello

 

we are trying to move from XPS/EDK to Vivado:

I succeeded at creating what we wanted in XPS but failed at using components like serdes/pll etc.. we hope to find an anwser in vivado. First of all I would like to recreate what I used to do concerning the axi_bus in xps:

 

here is a first helloworld thing I am trying to do: check the second design

the aim is to flash the leds with a command coming from the linux kernel, check if "wr_req" "rd_req" is toggled or not, change the logic etc..

 

 

we 've had two problems with java crashes which were solved by:

export LANG="en_US.UTF-8"      found on a report issues note
and "ip vendor" = (none)   '(' caused parsing problems, found on this forum.

I've been following this tutorial: check out the first design

I was getting errors like my reset were asynchronous and caused crash, this removed the error.
But this guy uses an "axi_periph" which seems no longer available
I found it more "natural" to try to use the axi interconnect with the axi general purpose port

 

Anyway, I hit "generate the block design" without troubles but synthesis failed with messages:

IP_FLOW 19 892 Detected invalid port type "wire" Port type connected to STD_LOGIC (or STD_LOGIC_VECTOR)

seems like a problem with my leds[7:0] wr_req & rd_req outs.

Failed to launch "impl_1" the following runs need to be reset first axi_interconnect_0_synth_1

I wasn't able to find an answer,

any clue would be appreciated..

thanks

gw.
Embedded Systems, DSP, cyber
example_design.png
my_design.png
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10 Replies
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Xilinx Employee
Xilinx Employee
8,096 Views
Registered: ‎07-01-2010

Hi,

What is the version of vivado you are using?
Can you try the latest version?

Regards,
Achutha
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8,093 Views
Registered: ‎03-27-2014

we are using Vivado 2014.1 installed about one month ago
gw.
Embedded Systems, DSP, cyber
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Scholar
Scholar
8,091 Views
Registered: ‎06-14-2012

Is the led IP your custom ip? You have to declare these as ports in your RTl? From the error its l.clear that wr_req & rd_re are defined as wires and not as top leve ports.

 

Kindly make these changes, Otherwise, if they are already defined as ports in your IP, please update.

 

Hope this helps.

 

Regards

Sikta

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8,087 Views
Registered: ‎03-27-2014

yes the led ip is the custom ip
excuse me if I wasn't clear enough

 

edit
Hum  are you talking about pure languages error? VHDL/Verilog?
I only use VHDL and so, everything is declared as ports and only ports.. ??

 

edit^2

During my ip creation and my ip "packaging", in the IP Ports interface, leds wr_req & rd_req are declared as ports,

leds is "std_logic_vector" and only std_logic for the latter, as expected.

gw.
Embedded Systems, DSP, cyber
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Scholar
Scholar
8,080 Views
Registered: ‎06-14-2012

No problem. Thanks for your explanation. Something is missing somewhere.

 

You should be able to add custom ports and wires inside your custom peripherals.

You can right click on your custom IP and open in editing session and then make your changes. Dont forget it to repackage it so that changes are reflected appropriately in the original block diagram. You can also refer the user guide for some more information.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug896-vivado-ip.pdf

 

 

Can you check ?

 

Regards

Sikta

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Xilinx Employee
Xilinx Employee
8,075 Views
Registered: ‎07-01-2010

Hi,

 

Can you open the custom IP .XML created in notepad and check if you find any wiretype defs in it?

 

Can you check by changing the main project target language to VHDL and see if the critical warning is seen?

 

 

Regards,

Achutha

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8,055 Views
Registered: ‎03-27-2014

Thanks for your advices.

There's a wire_type_def for every single port (axi_bus)

my "custom" ports are declared properly I think

check it out: component.xml

 

Edit:


OKAY so the problem seems to be solved, thanks for your help
We installed a "server license" at first,
my session was booted on this one & we never succeeded at generating anything with it.
one of my colleague switch it to a "node_blocked" license from the website and he succeeded.
I was using the older one  (or at least, all of my stuff never requiered synthisis yet)

I moved to the same licence with the manager, & synthisis is working now.

 

 

gw.
Embedded Systems, DSP, cyber
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Xilinx Employee
Xilinx Employee
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Registered: ‎07-01-2010

Hi,

I am little unsure on whether the issue is fixed here or not. Do you mean that currently you are able generate the block design and synthesize the design.

Regards,
Achutha
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7,995 Views
Registered: ‎03-27-2014

Yes i am!

The problem was the "server" license first installed didn't allow synthesis.
My colleague switched it to a nodeblocked license via the website, and I wasn't aware at first.

he could definately run helloworld designs on his session, but I could'nt since I still had the old license in my .Xilinx files.

Now that I moved to the new one,
I have already translated all of my work to vivado (~12h)& I can tell you it is a very very much better interface than XPS/EDK.
designing used to be painful especially the custom ip creation & import process (with the .mpd updates and stuff like that)


I have already demonstrated the libraries i mentioned can now  be instanciated without any trouble, at least in our configuration, so, i (& the team) am happy since all of our application will run without any trouble now :)

 

now let's get back to the code & developping new apps :p

gw.
Embedded Systems, DSP, cyber
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Anonymous
Not applicable
1,833 Views

Hi,

 

I'm facing the same issue in Vivado 2014.2 but I can assure that this has nothing to do with license.

We start developing our projet in Vivado 2013.3 but due to DSP limitation in KC705_325t, we need to upgrade our projet to VC707and we also update this projet to Vivado 2014.2.

 

The target language is set to VHDL although there are some custom IPs developed by us in verilog.

But the problem is not due to our custom IPs, it appears to be related with sub IPs from AXI Interconnect MEM (in our case, "system_xbar_X" and "system_auto_pc_X" components).

 

Here is an short example of the warnings we are facing:

 

[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_xbar_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
[IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_xbar_0' does not support 'VHDL Simulation' output products, delivering 'Verilog Simulation' output products instead.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_pc_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
[IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_pc_0' does not support 'VHDL Simulation' output products, delivering 'Verilog Simulation' output products instead.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC_VECTOR'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC'.
[IP_Flow 19-892] Detected invalid port type 'wire'. Port type corrected to 'STD_LOGIC'.
[IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_us_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead.
[IP_Flow 19-1687] The current project language is set to VHDL. However IP 'system_auto_us_0' does not support 'VHDL Simulation' output products, delivering 'Verilog Simulation' output products instead.

 

If I set the target language to verilog, this warnings don't seem to appear, so I think they are really related with the message "However IP 'system_auto_us_0' does not support 'VHDL Synthesis' output products, delivering 'Verilog Synthesis' output products instead."

 

I'm used to get warnings that some particular IP does not support one language and that its own files are delivered in ohter language...but I don't remember to see this "invalid port type" before.

 

Anyone confirms the same behaviour in Vivado 2014.2?

Could this be a problem?

 

Best regards.

 

SJuliao

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