We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎05-31-2017




I am trying to run xiicps_polled_master_example from Zynq7000 BSP which goes with Xilinx SDK. The problem I get is the NACK flag set which immediately returns IIC Master Polled Example Test Failed.


In my design I have one Zynq7000 Soc and ILA, which is used to trigger and record outputs from SDA and SCL lines from I2C0 interface. I2C0 lines goes over MIO14,15 pins. I2C SCL and SDA lines are always high, I read that it can represent idle state of i2c peripheral, am I right?


As it is stated in Zynq7000 Technical reference manual, to fulfill start condition we need to while the SCL line is high, have a transition from high to low on SDA line, but when I wrote in zero value byte in data register of i2c peripheral, SDA doesn't go low, why? what can be the cause?


I am just trying to see clock and some data sent on ILA, but without success. If you need some more informations, I will provide them.



Tags (1)
0 Kudos
1 Reply
Visitor david.600
Registered: ‎05-02-2017

Re: xiicps_polled_master_example

Did you manage to solve the issue?
0 Kudos