07-14-2011 03:03 AM
I have a problem when using the xps_tft to output to VGA. I have searched through the forums and Google but I haven't found any clue to solve it.
I have not enough internal memory for the xps_tft video memory (2 MB needed) so I have to use the external Micron RAM.
More information about the FPGA I'm using:
Digilent board datasheet: http://dl.dropbox.com/u/1809329/Xilinx/Nexys2_rm.pdf
Xilinx Spartan 3-e datasheet: http://dl.dropbox.com/u/1809329/Xilinx/ds312.pdf
This is the process I followed:
- I create a new project with BSB wizard, adding a 16 MB Micron RAM.
- Then I add the xps_tft IP:
> I configure it with "Select TFT interface" disabled, as I want to use the R, G, B, outputs.
> Base address of PLB Attached Video Memory: I set it as 0x82000000 (the same as the MicronRAM base address)
- Then I set the external ports, ucf pins, etc.
After a synthesis without errors, I make a C program to test the VGA output. Let's start by cleaning the screen and then let's write a pixel to see if it works... but here comes the problem. If I write a pixel (for example, the (0,0) where the first number is the row and the second one is the column), six pixels are shown (a vertical bar of pixels instead of a pixel).
What is happening is that he screen shows the first row repeated six times, then the second row... so if I write the first 80 rows, they fill the screen (80 x 6 = 480 rows). Let's see an image example in which I set the first row to red and the second row to green:
XTft_SetPixel(&TftInstance, 0, 0, 0x00FF0000); -> If I debug the program, this instruction writes the color value to the external memory base address 0x82000000. This seems to be OK, and the colums are well drawn to the VGA screen.
So, what could be the problem?
- EDK 11.4, also tested with 12.3 (both using the xps_tft 2.01a controller)
- Here is the EDK 11.4 project file if you want to check it (the C source code is in workspace\colores folder):
09-08-2012 05:41 AM
I got the same problem with you.
I'm using NEXYS3.
I think what matters is the external memory. In the xps_tft datasheet , using the mpmc ip core which is coresponding to sdram ddr, not cell ram in the nexys board.
06-04-2013 11:00 AM
I am seeing the same thing on my Nexys 3 using the cellular RAM. Did either of you resolve this issue? Is it related to cacheing? Please post what you changed to make it work. Thanks.
11-08-2015 12:30 PM
Did anyone solve this problem?
I have a similar problem on Nexys3 board. I've created simple microblaze system and added XPS_tft controler. After that, I've added xtft_example.c code from XPS_tft component examples to SDK project.
My problem is that I can see only 120 rows on monitor (0 - 119). After reading this post, I realized that, in my case, every pixel is shown with 4 pixels.
Any information will be useful.
If you need more details about my problem/project, please let me know.