UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie islandarmor
Newbie
4,541 Views
Registered: ‎11-08-2014

xtft ip on virtex 5 Lx50T stop at XTft_CfgInitialize line

Hello,

 

I have virtex5 xc5vlx50t and it has an HDMI output port

 

According to the reference manual of the board, it says I can use Xtft core with a HDMI to DVI adaptor to display text, color bar etc. on a monitor

 

I tried so many different BSB designs while trying to run the Xtft example but without any luck, Nothing is displayed on the monitor!!!

 

Every time I run the  xtft example, it seems the xtft example stuck at XTft_CfgInitialize line 

 

I don't know where the problem is, is it in the xtft example or in my design 

 

Anyway to figure out if my BSB design is working correctly before testing the xtft example? 

 

I really appreciate any suggestion 

 

Thanks

 

Here is the System.mhs

 

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd
# Sat Nov 08 17:05:39 2014
# Target Board:  Digilent Digilent Genesys System Board Rev C
# Family:    virtex5
# Device:    xc5vlx50t
# Package:   ff1136
# Speed Grade:  -1
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 125.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
 PARAMETER VERSION = 2.1.0


 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
 PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
 PORT fpga_0_FLASH_Mem_RPN_pin = fpga_0_FLASH_Mem_RPN_pin, DIR = O
 PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN_pin, DIR = O
 PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN_pin, DIR = O
 PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN_pin, DIR = O
 PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ_pin, DIR = IO, VEC = [0:15]
 PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CS_n_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr_pin, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin, DIR = IO, VEC = [7:0]
 PORT fpga_0_RS232_Uart_0_RX_pin = fpga_0_RS232_Uart_0_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_0_TX_pin = fpga_0_RS232_Uart_0_TX_pin, DIR = O
 PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT xps_mch_emc_0_Mem_LBON_pin = xps_mch_emc_0_Mem_LBON, DIR = O
 PORT xps_tft_0_TFT_HSYNC_pin = xps_tft_0_TFT_HSYNC, DIR = O
 PORT xps_tft_0_TFT_DE_pin = xps_tft_0_TFT_DE, DIR = O
 PORT xps_tft_0_TFT_DVI_CLK_P_pin = xps_tft_0_TFT_DVI_CLK_P, DIR = O
 PORT xps_tft_0_TFT_DVI_DATA_pin = xps_tft_0_TFT_DVI_DATA, DIR = O, VEC = [11:0]
 PORT xps_tft_0_TFT_DVI_CLK_N_pin = xps_tft_0_TFT_DVI_CLK_N, DIR = O
 PORT xps_tft_0_TFT_IIC_SCL = xps_tft_0_TFT_IIC_SCL, DIR = IO
 PORT xps_tft_0_TFT_IIC_SDA = xps_tft_0_TFT_IIC_SDA, DIR = IO
 PORT xps_tft_0_TFT_VSYNC_pin = xps_tft_0_TFT_VSYNC, DIR = O
 PORT xps_mch_emc_0_Mem_OEN_pin = xps_mch_emc_0_Mem_OEN, DIR = O, VEC = [0:1]
 PORT xps_mch_emc_0_Mem_CEN_pin = xps_mch_emc_0_Mem_CEN, DIR = O, VEC = [0:1]
 PORT DVI_reset_pin = proc_sys_reset_0_Peripheral_aresetn, DIR = O, SIGIS = RST, RST_POLARITY = 0


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER HW_VER = 8.20.b
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 2.00.b
 PORT LMB_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 2.00.b
 PORT LMB_Clk = clk_125_0000MHzPLL0
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_Uart_1_RX_pin
 PORT TX = fpga_0_RS232_Uart_1_TX_pin
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = FLASH
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CHANNELS = 0
 PARAMETER C_MEM0_WIDTH = 16
 PARAMETER C_MAX_MEM_WIDTH = 16
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 110000
 PARAMETER C_TAVDV_PS_MEM_0 = 110000
 PARAMETER C_THZCE_PS_MEM_0 = 35000
 PARAMETER C_TWC_PS_MEM_0 = 11000
 PARAMETER C_TWP_PS_MEM_0 = 70000
 PARAMETER C_TLZWE_PS_MEM_0 = 35000
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_MEM0_BASEADDR = 0x8a000000
 PARAMETER C_MEM0_HIGHADDR = 0x8bffffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RdClk = clk_125_0000MHzPLL0
 PORT Mem_A = 0b0000000 & fpga_0_FLASH_Mem_A_pin_vslice_7_30_concat & 0b0
 PORT Mem_RPN = fpga_0_FLASH_Mem_RPN_pin
 PORT Mem_CEN = fpga_0_FLASH_Mem_CEN_pin
 PORT Mem_OEN = fpga_0_FLASH_Mem_OEN_pin
 PORT Mem_WEN = fpga_0_FLASH_Mem_WEN_pin
 PORT Mem_DQ = fpga_0_FLASH_Mem_DQ_pin
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR2_SDRAM
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_NUM_IDELAYCTRL = 3
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y5-IDELAYCTRL_X0Y1-IDELAYCTRL_X0Y0
 PARAMETER C_MEM_PARTNO = mt4htf3264h-53e
 PARAMETER C_MEM_ODT_TYPE = 1
 PARAMETER C_MEM_CLK_WIDTH = 2
 PARAMETER C_MEM_ODT_WIDTH = 2
 PARAMETER C_MEM_CE_WIDTH = 2
 PARAMETER C_MEM_CS_N_WIDTH = 2
 PARAMETER C_DDR2_DQSN_ENABLE = 1
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER HW_VER = 6.05.a
 PARAMETER C_SDMA1_PI2LL_CLK_RATIO = 1
 PARAMETER C_PIM1_BASETYPE = 3
 PARAMETER C_MPMC_BASEADDR = 0x90000000
 PARAMETER C_MPMC_HIGHADDR = 0x9fffffff
 PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
 PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff
 BUS_INTERFACE SPLB0 = mb_plb
 BUS_INTERFACE SDMA_CTRL1 = mb_plb
 PORT MPMC_Clk0 = clk_125_0000MHzPLL0
 PORT MPMC_Clk0_DIV2 = clk_62_5000MHzPLL0
 PORT MPMC_Clk90 = clk_125_0000MHz90PLL0
 PORT MPMC_Clk_200MHz = clk_200_0000MHz
 PORT MPMC_Rst = sys_periph_reset
 PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DDR2_Clk_pin
 PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin
 PORT DDR2_CE = fpga_0_DDR2_SDRAM_DDR2_CE_pin
 PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DDR2_CS_n_pin
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
 PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin
 PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin
 PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DDR2_WE_n_pin
 PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin
 PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DDR2_Addr_pin
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
 PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin
 PORT SDMA1_Clk = clk_125_0000MHz90PLL0
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_0
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x84020000
 PARAMETER C_HIGHADDR = 0x8402ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_Uart_0_RX_pin
 PORT TX = fpga_0_RS232_Uart_0_TX_pin
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKOUT0_FREQ = 125000000
 PARAMETER C_CLKOUT0_PHASE = 90
 PARAMETER C_CLKOUT0_GROUP = PLL0
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 125000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 200000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = NONE
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 62500000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = PLL0
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_CLKOUT4_FREQ = 25000000
 PORT CLKIN = CLK_S
 PORT CLKOUT0 = clk_125_0000MHz90PLL0
 PORT CLKOUT1 = clk_125_0000MHzPLL0
 PORT CLKOUT2 = clk_200_0000MHz
 PORT CLKOUT3 = clk_62_5000MHzPLL0
 PORT RST = sys_rst_s
 PORT LOCKED = Dcm_all_locked
 PORT CLKOUT4 = clock_generator_0_CLKOUT4
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 3.00.a
 PORT Slowest_sync_clk = clock_generator_0_CLKOUT4
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = Dcm_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
 PORT Peripheral_aresetn = proc_sys_reset_0_Peripheral_aresetn
END

BEGIN xps_tft
 PARAMETER INSTANCE = xps_tft_0
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_DCR_SPLB_SLAVE_IF = 1
 PARAMETER C_TFT_INTERFACE = 1
 PARAMETER C_I2C_SLAVE_ADDR = 0b1110110
 PARAMETER C_DEFAULT_TFT_BASE_ADDR = 0x90000000
 PARAMETER C_SPLB_BASEADDR = 0x86e00000
 PARAMETER C_SPLB_HIGHADDR = 0x86e0ffff
 BUS_INTERFACE MPLB = mb_plb
 BUS_INTERFACE SPLB = mb_plb
 PORT SYS_TFT_Clk = clock_generator_0_CLKOUT4
 PORT TFT_HSYNC = xps_tft_0_TFT_HSYNC
 PORT TFT_DE = xps_tft_0_TFT_DE
 PORT TFT_DVI_CLK_P = xps_tft_0_TFT_DVI_CLK_P
 PORT TFT_DVI_DATA = xps_tft_0_TFT_DVI_DATA
 PORT TFT_DVI_CLK_N = xps_tft_0_TFT_DVI_CLK_N
 PORT TFT_IIC_SCL = xps_tft_0_TFT_IIC_SCL
 PORT TFT_IIC_SDA = xps_tft_0_TFT_IIC_SDA
 PORT TFT_VSYNC = xps_tft_0_TFT_VSYNC
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = xps_mch_emc_0
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_NUM_BANKS_MEM = 2
 PARAMETER C_MEM1_WIDTH = 16
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_1 = 1
 PARAMETER C_TAVDV_PS_MEM_1 = 110000
 PARAMETER C_THZCE_PS_MEM_1 = 35000
 PARAMETER C_THZOE_PS_MEM_1 = 15000
 PARAMETER C_TWC_PS_MEM_1 = 110000
 PARAMETER C_TWP_PS_MEM_1 = 70000
 PARAMETER C_TLZWE_PS_MEM_1 = 35000
 PARAMETER C_MEM0_BASEADDR = 0x8d000000
 PARAMETER C_MEM0_HIGHADDR = 0x8d0fffff
 PARAMETER C_MEM1_BASEADDR = 0x8e000000
 PARAMETER C_MEM1_HIGHADDR = 0x8fffffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Mem_LBON = xps_mch_emc_0_Mem_LBON
 PORT Mem_OEN = xps_mch_emc_0_Mem_OEN
 PORT Mem_CEN = xps_mch_emc_0_Mem_CEN
 PORT RdClk = clk_125_0000MHz90PLL0
END

 

 

 

 

Here is the xtft example 

 

/*$Id: xtft_example.c,v 1.1.2.1 2009/11/25 08:14:26 svemula Exp $ */
/******************************************************************************
*
* (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information of Xilinx, Inc.
* and is protected under U.S. and international copyright and other
* intellectual property laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any rights to the
* materials distributed herewith. Except as otherwise provided in a valid
* license issued to you by Xilinx, and to the maximum extent permitted by
* applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL
* FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS,
* IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
* MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE;
* and (2) Xilinx shall not be liable (whether in contract or tort, including
* negligence, or under any other theory of liability) for any loss or damage
* of any kind or nature related to, arising under or in connection with these
* materials, including for any direct, or any indirect, special, incidental,
* or consequential loss or damage (including loss of data, profits, goodwill,
* or any type of loss or damage suffered as a result of any action brought by
* a third party) even if such damage or loss was reasonably foreseeable or
* Xilinx had been advised of the possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-safe, or for use in
* any application requiring fail-safe performance, such as life-support or
* safety devices or systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any other applications
* that could lead to death, personal injury, or severe property or
* environmental damage (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and liability of any use of
* Xilinx products in Critical Applications, subject only to applicable laws
* and regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
* AT ALL TIMES.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xtft_example.c
*
* This file contains a design example using the driver functions of the XTft
* driver. This example shows the usage of the driver/device to
* - Write a character and write a string of characters
* - Draw a line
* - Turn ON/OFF the TFT Device
*
*
* @note
*
* TFT_FRAME_ADDR specifies the starting address of the 2MB space for storing the
* frame data and has to be defined by the user based on the system memory map.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver    Who   Date      Changes
* -----  ----  --------  -----------------------------------------------
* 1.00a  sg    03/24/08  First release
* 1.00a  sg    09/24/08  Updated the example to update the Video Memory Base
*			 Address with the Memory specified by the application
* 2.00a  ktn   07/09/09  Updated the example to poll the Vsync(Video address
*			 latch) status bit before writing to the Address
*			 Register (AR)
* </pre>
*
*****************************************************************************/

/***************************** Include Files ********************************/

#include "xtft.h"
#include "xparameters.h"

/************************** Constant Definitions ****************************/
/**
 * The following constants map to the XPAR parameters created in the
 * xparameters.h file. They are defined here such that a user can easily
 * change all the needed parameters in one place.
 */
#define TFT_DEVICE_ID	XPAR_TFT_0_DEVICE_ID

/**
 * User has to specify a 2MB memory space for filling the frame data.
 * This constant has to be updated based on the memory map of the
 * system.
 */
//#define TFT_FRAME_ADDR		XPAR_MPMC_0_MPMC_HIGHADDR - 0x001FFFFF
#define TFT_FRAME_ADDR		XPAR_MPMC_0_MPMC_HIGHADDR - 0x9FFFFFFF
/**************************** Type Definitions ******************************/

/***************** Macros (Inline Functions) Definitions ********************/

/**
 * Color Values.
 */
#define FGCOLOR_VALUE		0x0000FF00	/**< Foreground Color - Green */
#define BGCOLOR_VALUE		0x0		/**< Background Color - Black */
#define WHITECOLOR_VALUE 	0x00FFFFFF	/**< Color - White */

/**
 * Start and End point Coordinates for the line.
 */
#define X1POS	100	/**< Column Start Position */
#define X2POS	100	 /**< Column End Position */
#define Y1POS	50 	/**< Row Start Position */
#define Y2POS	450	 /**< Row End Position */

/************************** Function Prototypes *****************************/

static int TftWriteString(XTft *InstancePtr, const u8 *CharValue);
static int TftDrawLine(XTft *InstancePtr, u32 ColStartPos, u32 RowStartPos,
			u32 ColEndPos, u32 RowEndPos, u32 PixelVal);
int TftExample(u32 TftDeviceId);

/************************** Variable Definitions ****************************/

static XTft TftInstance;
//set to 1 in order to display debug messages
unsigned char verbose=0;
#define DISPLAY_ROW_BUFFER_WIDTH 1024
#define DISPLAY_COLUMNS  640
#define DISPLAY_ROWS     480
/************************** Function Definitions ****************************/
/*****************************************************************************/
/**
*
* Main function that invokes the Tft example.
*
* @param	None.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_FAILURE if unsuccessful.
*
* @note		None.
*
******************************************************************************/
int main()
{
	int Status;
	print(" main enter \n\r");
	Status = TftExample(TFT_DEVICE_ID);
	if ( Status != XST_SUCCESS) {
		print(" main failed \n\r");
		return XST_FAILURE;
	}
	print(" main SUCCESS \n\r");

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
*
* This is the example function which performs the following operations on
* the TFT device -
* - Set the color values of foreground and background
* - Write two characters (S) one after another
* - Write a string of characters
* - Draw a line and scroll the screen once
* - Disable the display (The screen goes blank)
* - Scroll the screen once and draw a line
* - Enable the TFT display
*
* @param	TftDeviceId is the unique Id of the device.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_FAILURE if unsuccessful.
*
* @note		None.
*
******************************************************************************/
int TftExample(u32 TftDeviceId)
{
	int Status;
	u8 VarChar;
	XTft_Config *TftConfigPtr;

	Xuint32 i;
	   Xuint32 color_data;

	/*
	 * Get address of the XTft_Config structure for the given device id.
	 */
	print(" TftExample Enter \n\r");
	TftConfigPtr = XTft_LookupConfig(TftDeviceId);
	if (TftConfigPtr == (XTft_Config *)NULL) {
		print(" TftConfigPtr XST_FAILURE \n\r");
		return XST_FAILURE;
	}
	print(" TftConfigPtr SUCCESS \n\r");
	/*
	 * Initialize all the TftInstance members and fills the screen with
	 * default background color.
	 */
	print("XTft_CfgInitialize before \n\r");
	Status = XTft_CfgInitialize(&TftInstance, TftConfigPtr,
				 	TftConfigPtr->BaseAddress);

	print("After XTft_CfgInitialize ");
	if (Status != XST_SUCCESS) {
		print("XTft_CfgInitialize FAILURE \n\r");
		 if (verbose) print("\r\nError in TFT cfginitialize");
		return XST_FAILURE;
	}
	print("XTft_CfgInitialize SUCCESS \n\r");
	/*
	 * Wait till Vsync(Video address latch) status bit is set before writing
	 * the frame address into the Address Register. This ensures that the
	 * current frame has been displayed and we can display a new frame of
	 * data. Checking the Vsync state ensures that there is no data flicker
	 * when displaying frames in real time though there is some delay due to
	 * polling.
	 */
	print("XTft_GetVsyncStatus before \n\r");
	while (XTft_GetVsyncStatus(&TftInstance) !=
					XTFT_IESR_VADDRLATCH_STATUS_MASK);

	/*
	 * Change the Video Memory Base Address from default value to
	 * a valid Memory Address and clear the screen.
	 */
	print("XTft_SetFrameBaseAddr after \n\r");
	XTft_SetFrameBaseAddr(&TftInstance, TFT_FRAME_ADDR);
	print("XTft_SetFrameBaseAddr after \n\r");
	XTft_ClearScreen(&TftInstance);
	print("XTft_ClearScreen after \n\r");



	XTft_SetColor(&TftInstance, 0x00ffffff, 0);

	    //Display a colorbar pattern
	    if (verbose) xil_printf("  Writing Color Bar Pattern\r\n");
	    for (i=0; i <640; i=i+1)
	     {
	        if (i<213)  color_data=(i+42) << 16;
	        else if ((i>213)&&(i<426)) color_data=(i-213+42)<<8;
	        else if (i>426) color_data=(i-426+42);
	        //color_data=0;
	       XTft_FillScreen(&TftInstance,  i, 0, i,479,color_data);
	     }

	     //write a text on the screen
	    if (verbose) xil_printf ("\r\nWriting Text");
	      XTft_SetPos(&TftInstance, 280, 200);
	    Status = TftWriteString(&TftInstance, (u8*)"G E N E S Y S");
	   XTft_SetPos(&TftInstance, 240, 220);
	    Status = TftWriteString(&TftInstance, (u8*)"C O L O R B A R  D E M O");




	/*
	 * Initialize the variable VarChar to the value to be displayed on the
	 * screen.
	 * Set the foreground and background colors.
	 */
	VarChar = 'S';
	XTft_SetColor(&TftInstance, FGCOLOR_VALUE, BGCOLOR_VALUE);
	print(" XTft_SetColor \n\r");

	/*
	 * Write the character two times starting from top left corner
	 * (i.e. origin) of screen.
	 */
	XTft_Write(&TftInstance, VarChar);
	XTft_Write(&TftInstance, VarChar);
	print(" XTft_Write \n\r");

	/*
	 * Write a string which is displayed next to the two characters
	 * written previously.
	 */
	Status = TftWriteString(&TftInstance, (u8*)"TFT CONTROLLER\n");

	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	print(" TftWriteString success \n\r");
	/*
	 * Draw a line between the coordinates (X1,Y1) and (X2,Y2) which
	 * displays a vertical line in white color.
	 * Scroll the screen, so the two characters and string will be
	 * erased on screen.
	 */
	Status = TftDrawLine(&TftInstance, X1POS, Y1POS, X2POS, Y2POS,
				WHITECOLOR_VALUE);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	print(" TftDrawLine success \n\r");
	XTft_Scroll(&TftInstance);

	/*
	 * Disable the display, the screen will be turned off.
	 */
	XTft_DisableDisplay(&TftInstance);

	/*
	 * Even though the screen is turned off, we can still do operations on
	 * video memory.
	 * Scroll the screen.
	 * Draw a line between the coordinates (X1 + 10,Y1) and (X2,Y2) which
	 * is displayed at different position as X1 has some offset.
	 */
	XTft_Scroll(&TftInstance);
	Status = TftDrawLine(&TftInstance, X1POS + 10, Y1POS, X2POS + 10,
				 Y2POS, WHITECOLOR_VALUE);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Enable the display. Screen will display two lines in white color.
	 * The first line from the left of screen is slightly above the
	 * second one indicating the scroll was successful.
	 */
	XTft_EnableDisplay(&TftInstance);

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
* Write a string of characters to the TFT.
*
* @param	InstancePtr is a pointer to the XTft instance.
* @param	CharValue is a pointer to the character array to be written
*		to the TFT screen.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_FAILURE if unsuccessful.
*
* @note		None.
*
******************************************************************************/
static int TftWriteString(XTft *InstancePtr, const u8 *CharValue)
{
	/*
	 * Writes a character from the string to the screen
	 * until it reaches null or end of the string.
	 */
	while (*CharValue != 0) {
		XTft_Write(InstancePtr, *CharValue);
		CharValue++;
	}

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
* Draws a line between two points with a specified color.
*
* @param	InstancePtr is a pointer to the XTft instance.
* @param	ColStartPos is the Start point of Column.
*		The valid value is 0 to (XTFT_DISPLAY_WIDTH - 1).
* @param	RowStartPos is the Start point of Row.
*		The valid value is 0 to (XTFT_DISPLAY_HEIGHT - 1).
* @param	ColEndPos is the End point of Column.
*		The valid value is 0 to (XTFT_DISPLAY_WIDTH - 1).
* @param	RowEndPos is the End point of Row.
*		The valid value is 0 to (XTFT_DISPLAY_HEIGHT - 1).
* @param	PixelVal is the Color Value to be put at pixel.
*
* @return
*		- XST_SUCCESS if successful.
*		- XST_FAILURE if unsuccessful.
*
* @note		None.
*
******************************************************************************/
static int TftDrawLine(XTft *InstancePtr, u32 ColStartPos, u32 RowStartPos,
			u32 ColEndPos, u32 RowEndPos, u32 PixelVal)
{
	u32 Slope;
	u32 YIntercept;
	u32 Xmin;
	u32 Ymin;
	u32 Xmax;
	u32 Ymax;
	u32 Index1;
	u32 Index2;
	u32 Mx;

	/*
	 * Check whether the given position of X,Y dimensions
	 * are below the limits of the screen.
	 */
	if (ColStartPos >= 0 && ColStartPos <= (XTFT_DISPLAY_WIDTH - 1) &&
		ColEndPos >= 0 && ColEndPos <= (XTFT_DISPLAY_WIDTH - 1) &&
		RowStartPos >= 0 && RowStartPos <= (XTFT_DISPLAY_HEIGHT - 1) &&
		RowEndPos >= 0 && RowEndPos <= (XTFT_DISPLAY_HEIGHT - 1)) {

		/*
		 * Check the exception case where slope can be infinite
		 * that is vertical line.
		 */
		if (ColEndPos-ColStartPos != 0) {
			/*
			 * Calculate slope.
			 */
			Slope = ((RowEndPos - RowStartPos) /
				(ColEndPos - ColStartPos) * 100000);

			/*
			 * Calculate y intercept.
			 */
			YIntercept = RowStartPos -
					((Slope / 100000) * ColStartPos);
		} else {
			/*
			 * Divide by zero.
			 */
			Slope = 0;
			YIntercept = (-1);
		}

		/*
		 * Update the min and max position by conditional checking.
		 */
		if (ColEndPos < ColStartPos) {
			Xmin = ColEndPos;
			Xmax = ColStartPos;
		} else {
			Xmin = ColStartPos;
			Xmax = ColEndPos;
		}
		if (RowEndPos < RowStartPos) {
			Ymin = RowEndPos;
			Ymax = RowStartPos;
		} else {
			Ymin = RowStartPos;
			Ymax = RowEndPos;
		}

		/*
		 * Increment X and Y position values and calculate
		 * slope at the corresponding x position. Check the condition
		 * for general line equation and set the pixel. Otherwise check
		 * for the case of vertical line.
		 */
		for (Index1 = Xmin; Index1 <= Xmax; Index1++) {
			Mx = (Slope * Index1) / 100000;
			for (Index2 = Ymin; Index2 <= Ymax; Index2++) {
				if ((Index2 - Mx) == YIntercept) {

					/*
					 * Calculate visible line.
					 */
					XTft_SetPixel(InstancePtr, Index1,
						 Index2, PixelVal);
				}
				else {
					/*
					 * Divide by zero.
					 */
					if((Slope == 0) &&
							(YIntercept == -1)) {

						/*
						 * Vertical line.
						 */
						XTft_SetPixel(InstancePtr,
							Index1, Index2,
							PixelVal);
					}
				}
			}
		}
		return XST_SUCCESS;
	} else {
		return XST_FAILURE;
	}

}

 

 

 

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
4,534 Views
Registered: ‎08-02-2007

Re: xtft ip on virtex 5 Lx50T stop at XTft_CfgInitialize line

Hi,

 

Do a quick comparison between the way TFT is configured in your system and compare it with this reference design.

http://www.xilinx.com/products/boards/ml505/ml505_11.1_1/docs/ml505_bsb_std_ip_addition.pdf

 

--Hem

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos