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Registered: ‎07-18-2019

xuartps_intr_exemple Arty Z7 interrupt not triggered

Hi,

I have a very simple design created with the official Digilent board file :

Capture.PNG

 

uart0 is enabled.

In Vitis, I have created the BSP and imported the xuartps_intr_exemple project.

When I debug the project, everything seems to execute fine without a failure, but the interrupt never seem to trigger making the example hang in the while loop.

Is there a manipulation I am missing?

Thank you.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-06-2016

Hi @cntoinecreaform 

The block design looks OK, from Vivado point of view the only thing you need is to have the correspondent UART enabled. How are you loading the example in the device? Using Vitis/SDK? Can you share your debug configuration?

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
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