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Registered: ‎07-27-2015

zynqMP 19EG project with multiple PL DDR4, the HDF file incorrect.


   I am using the zu19EG to design a system with two DDR4s that connect to PL. My Vivado version is 2018.3.

   At beginning, our projects is divided into two projects. One project only contained the test functions for two DDR4s (without PS block design), two DDRs test have passed, read or write all worked well. The other only contained block design that has PS part(with ps ddr4), PCS IP core, and it also worked well.

   Then I combine the tow projects as one. After I generate the bitstream and export the hardware design, I launch the SDK , the SDK log display the error as:

SDK logSDK log 

Then I open the hdf file with winrar, the files inside the hdf as follow shotscreen, just 5 files inside:


When I comment one of the PL DDR4s (or the other one) , the generated hdf file looks like correct, the SDK have no error, and the files in hdf as follow:


  Someone could help me? I have no ideal anymore for this odd problem, in my opinion, the hdf file only include the infomations about PS. The DDR4 in the PL that have no connections to PS  is independent, it cant affect the hdf file.

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Xilinx Employee
Xilinx Employee
Registered: ‎09-12-2007

Can you send the block_design_bd.tcl so I can test this?

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