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Voyager
Voyager
2,276 Views
Registered: ‎07-28-2008

zynqmp how to SDK step through bsp code (2017.1)

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I am learning xapp1306, created a bsp with FSBL generation, and made a new app based on the bsp.

 

After setting "-O0 -g3" in bsp build, the FSBL app failed with not enough memory (OCM) error.

My A53 standalone app still steps into assembly.

 

A53 application with regular bsp generation, stepping through bsp is fine.

 

So I need to understand how to step into bsp made with FSBL, or maybe how to reduce the bsp size, or move bsp somewhere else with more memory.

 

Please comment,

 

Thanks,

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Xilinx Employee
Xilinx Employee
3,415 Views
Registered: ‎02-01-2008

If you are having problems single stepping through FSBL and the FSBL bsp, then it is because LTO (link time optimization) is enabled. This option has been enabled in order to reduce the memory footprint of FSBL so that it can fit in a portion of OCM.

 

It is possible to disable LTO and reduce the fsbl BSP to -O2 and possibly fit in memory (dependent on what options you are using in fsbl).

 

Disable LTO and change optimization on BSP:

- right click on fsbl_bsp, select board_support_package_settings, select overview->standalone, change zynqmp_fsbl_bsp to false

- select overview->drivers->psu_cortex53->extra_compiler_flags, change -Os to -O2, and remove -flto and remove --ffat-lto-objects

- ok

- The above provides a .elf that fits in memory

 

To go further, disable LTO and change optimization on app:

- right click on fsbl, select C/C++ settings

- remove -Os, -flto and -ffat-lto-objects from ARM A53 gcc compiler->Miscellaneous->other_flags

- note that ARM A53 gcc compiler->optimization is set to -O0.

- note that fsbl will not fit in ocm at this point.

 

Reduce FSBL code size:

- edit fsbl->src->xfsb_config.h and change the following defines to exclude the code:

FSBL_NAND_EXCLUDE_VAL (1U)

FSBL_QSPI_EXCLUDE_VAL (1U)

FSBL_SECURE_EXCLUDE_VAL (1U)

 

Now, fsbl should fit in OCM. You can play around with these exclude values depending on what features of FSBL you require.

 

 

 

 

 

 

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Moderator
Moderator
2,214 Views
Registered: ‎10-06-2016

Hi @legendbb

 

After reading your post I'm not still sure where the problem is, I mean compiling the FSBL in OCM or step into the BSP code, can you clarify this? I guss that it might by a mix of both (compiling code in O0 to be able to debug the FSBL) but would be great to clarify it :)

 

Regards


Ibai
Don’t forget to reply, kudo, and accept as solution.
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Voyager
Voyager
2,208 Views
Registered: ‎07-28-2008
Thanks for attention, and sorry for not being clear in the first post.

1. I don't know, for xapp1306 setup, if the bsp has to be the one generated with FSBL creation.
2. I understood, the bsp generated with FSBL creation sits in OCM, which has not enough space if "-O0 -g3 " is turned on.
3. I have no problem stepping through regular bsp (created with app generation).
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Moderator
Moderator
2,200 Views
Registered: ‎10-06-2016

Hi @legendbb

 

I did not really tested the XAPP1306 but as long as the FSBL code is the same for any hardware project, it's bit strange to not be able to compile it in debug mode.

 

Are you using the default standalone BSP for the FSBL application? I mean if you enable extra libraries a would expect to not fit in OCM but otherwise it should be fit.

 

Can you share your HDF file to test it quickly on my side?


Regards

Ibai


Ibai
Don’t forget to reply, kudo, and accept as solution.
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Xilinx Employee
Xilinx Employee
3,416 Views
Registered: ‎02-01-2008

If you are having problems single stepping through FSBL and the FSBL bsp, then it is because LTO (link time optimization) is enabled. This option has been enabled in order to reduce the memory footprint of FSBL so that it can fit in a portion of OCM.

 

It is possible to disable LTO and reduce the fsbl BSP to -O2 and possibly fit in memory (dependent on what options you are using in fsbl).

 

Disable LTO and change optimization on BSP:

- right click on fsbl_bsp, select board_support_package_settings, select overview->standalone, change zynqmp_fsbl_bsp to false

- select overview->drivers->psu_cortex53->extra_compiler_flags, change -Os to -O2, and remove -flto and remove --ffat-lto-objects

- ok

- The above provides a .elf that fits in memory

 

To go further, disable LTO and change optimization on app:

- right click on fsbl, select C/C++ settings

- remove -Os, -flto and -ffat-lto-objects from ARM A53 gcc compiler->Miscellaneous->other_flags

- note that ARM A53 gcc compiler->optimization is set to -O0.

- note that fsbl will not fit in ocm at this point.

 

Reduce FSBL code size:

- edit fsbl->src->xfsb_config.h and change the following defines to exclude the code:

FSBL_NAND_EXCLUDE_VAL (1U)

FSBL_QSPI_EXCLUDE_VAL (1U)

FSBL_SECURE_EXCLUDE_VAL (1U)

 

Now, fsbl should fit in OCM. You can play around with these exclude values depending on what features of FSBL you require.

 

 

 

 

 

 

View solution in original post

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Voyager
Voyager
2,192 Views
Registered: ‎07-28-2008
Thanks a lot for offering testing, I enabled lwip. And I can understand if OCM won't fit.

I'm curious for xapp1306, if bsp won't fit in OCM. What happens if I just use regular bsp in DDR?
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