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kharalan
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Registered: ‎09-27-2018

2018.2 PL device tree generator syntax error

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Hi,

I'm trying to generated petalinux device tree based on the attched hdf file (ZCU102 board).

The device tree generates with some warnings:

WARNING: Frequency 33.330 used instead of 33.333
WARNING: ERROR: DMA_CH0_axi_dma: s2mm_introut port is not connected
WARNING: not supported pl_clk:
WARNING: ERROR: DMA_CH1_axi_dma: s2mm_introut port is not connected
WARNING: not supported pl_clk:

 

The IRQ warnings/errors are OK (the interrupts are not directly connected to the PS and we have custom DMA driver).

The pl_clk is most likely the s2mm clock form the JESD204B IP core.

The problem is the generated device tree pl.dtsi has syntax error in the clocks parameter and petalinux-build fails:

DMA_CH0_axi_dma: dma@b0001000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_s2mm_aclk";
clocks = <&clk 71>, <&clk 71>, <&>, <&misc_clk_0>;
compatible = "xlnx,axi-dma-1.00.a";
reg = <0x0 0xb0001000 0x0 0x1000>;
xlnx,addrwidth = <0x20>;
xlnx,include-sg ;
xlnx,sg-length-width = <0x17>;
dma-channel@b0001030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
};
};

 

misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <122880000>;
compatible = "fixed-clock";
};

 

Any idea, what can cause the device tree generator error?

Any idea how to work around this - I'm already overlaying some of the DMA parameters in system-user.dtsi, but petalinux-build is trying to compile pl.dtsi first and fails before reaching the overlay. I need to somehow fix pl.dtsi which is automatically generated by petalinux-build.

Thanks! 

1 Solution

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baf2099
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3,354 Views
Registered: ‎03-17-2017

I found another forum post with a similar issue...

 

https://forums.xilinx.com/t5/Embedded-Linux/pl-dtsi-syntax-error-with-DMA-Zynq-Ultrascale-2018-1-Tools/m-p/878114/highlight/true#M27713

 

It refers people to AR#71136 which supposedly can remedy the issue via a patch. I will try this and update whether this works or not

View solution in original post

6 Replies
baf2099
Adventurer
Adventurer
3,358 Views
Registered: ‎03-17-2017

I am having the same exact issue. Not having any luck with a workaround yet, hoping this post will get some visibility from a Xilinx employee.

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baf2099
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Adventurer
3,355 Views
Registered: ‎03-17-2017

I found another forum post with a similar issue...

 

https://forums.xilinx.com/t5/Embedded-Linux/pl-dtsi-syntax-error-with-DMA-Zynq-Ultrascale-2018-1-Tools/m-p/878114/highlight/true#M27713

 

It refers people to AR#71136 which supposedly can remedy the issue via a patch. I will try this and update whether this works or not

View solution in original post

baf2099
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Registered: ‎03-17-2017

So the good news is that the patch should get you through the pl.dtsi syntax errors, but beware that the clock and interrupt device tree entries will still be invalid and need overriding with the system-user.dtsi. Hopefully Xilinx will not just blindly apply this patch to 2018.3, but also fix the bad interrupt and clock references.

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jpeel@impinj.com
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Registered: ‎09-10-2018

 

I have a similar failure for the device-tree build, so I thought I would jump on this thread vs. starting a new one.

 

I'm running the 2018.2 tools for a Zynq-7000.  And I have a design that has a clock wizard IP block in it that is using an external clock as its reference (only for the PLL reference).  If I build the design without dynamic reconfig, the device tree generates just fine (a few DMA blocks, and a GPIO block).  However, if I do add dynamic reconfig to the clock wizard (with the AXI interface being clocked by Fclk_clk0), the device-tree generate gives the following error.

 

can't read "clkk": no such variable
ERROR: [Hsi 55-1545] Problem running tcl command ::sw_axi_clk_wiz::generate : can't read "clkk": no such variable
    while executing
"switch $clkk {
                        "FCLK_CLK0" {
                                        set fclk_clk0 "clkc 15"
                                        set clocks [lappend clocks $fclk_clk0]
                        }
                        "FCLK_CLK1" {
                                        set fclk_clk1 "clk..."
    ("foreach" body line 11)
    invoked from within
"foreach clk $clk_pins {
                set ip [get_cells -hier $drv_handle]
                set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $ip $clk]]..."
    (procedure "update_zynq_clk_wiz_node" line 6)
    invoked from within
"update_zynq_clk_wiz_node $drv_handle "clk_in1 s_axi_aclk""
    (procedure "::sw_axi_clk_wiz::generate" line 31)
    invoked from within
"::sw_axi_clk_wiz::generate clk_wiz_96"
ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()
generate_target failed
    while executing
"error "generate_target failed""
    invoked from within
"if {[catch {hsi generate_target -dir $project} res]} {
        error "generate_target failed"
}"

 

Any thoughts ?  Or maybe yet another patch :)

 

Also as a follow on.. I don't want the kernel to control this clock (I want to control it from a user space program).  Is the proper procedure to append something to the device tree that deletes the module in a bbappend recipe ?

 

Attached is the hdf file, and the log with the failure in it.

 

Thanks!

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baf2099
Adventurer
Adventurer
3,300 Views
Registered: ‎03-17-2017

That definitely sounds like a unique issue to me. The code that is failing you can be referenced here https://github.com/Xilinx/device-tree-xlnx/blob/master/axi_clk_wiz/data/axi_clk_wiz.tcl but there are likely other scripts or variables involved with your particular issue. I'd highly recommend you open up a new thread and detail this issue, especially since this forum post now has an accepted answer. Xilinx is very helpful when you give them a project that consistently fails in an obvious way so make sure to provide that zip file again. Best of luck!

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jpeel@impinj.com
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Registered: ‎09-10-2018

Gotcha

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