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beni.falk
Participant
Participant
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Registered: ‎01-05-2020

A high-resolution monotonic clock consistent across APU cores

We are running Linux in SMP mode on the RFSOC APU (using Linux provided with PetaLinux 2019.2).

I need a monotonic high-resolution (1 us or better) clock that can be read by application software with minimal overhead. It must be consistent across all APU cores.

Architecturally, it seems that ARM system counter provides the necessary features.

In the case of A53 the system counter does not reside within the A53 cores, instead it is provided by the SOC (ref. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500e/BABIGHII.html).

Indeed, UG1085 (v2.1) page 398 says the following:

Physical Counter

Each APU core includes a physical counter that contains the count value of the system counter. The CNTPCT register holds the current physical counter value. The CNTPCT counter operates in the LPD power domain to provide a reliable and uniform view of the system time to each of the APU cores.

Software with sufficient privilege can read CNTPCT using a 64-bit system control register read.

I have the following questions:

1. Does Linux for the RFSOC provides a clock (CLOCK_MONOTONIC / CLOCK_MONOTONIC_COARSE / CLOCK_MONOTONIC_RAW / CLOCK_BOOTTIME) that is guaranteed to be consistent across all APU cores?

2. If it does not:

2.1 Assuming that I should use the above counter (the one accessible via the CNTPCT register), what is its frequency on the RFSOC?

2.2 Is there an API for reading this counter he from application (non-kernel) code? If yes, does it involve a system call, or is it implemented in the Linux VDSO?

Thanks,

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beni.falk
Participant
Participant
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Registered: ‎01-05-2020

I now understand that CNTPCT is probably unreadable in EL0 (which is, according to my understanding, the exception level of user mode programs running under Linux).

However the architecture also comprises the following: CNTPCT_EL0, CNTVCT_EL0

I have the following questions:

a) Can one or more of the above counters be read from EL0 without trapping?

b) Is CNTVCT consistent across cores?

c) Does Linux ever modify the virtual counter offset (CNTVOFF)?

Thanks,

 

joe306
Scholar
Scholar
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Registered: ‎12-07-2018

Hello, did you get an answer to your post? 

I'm using the following code to measure how long a read takes on the A53 running at 1.2GHz.

Data_latency.jpg

The difference in the Timer read is 12. Is that 12 A53 Core clocks? 

I've seen the post:

https://www.xilinx.com/support/answers/66568.html

So maybe it is 12 1/2 A53 Core clock. So that would be 12 * (1/600Mhz).

Thank you

Joe

 

 

beni.falk
Participant
Participant
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Registered: ‎01-05-2020

Joe, 

I didn't actually get an answer to my question from Xilinx. 

Regarding the code that you have posted:

a) Is this code usable on Linux (as opposed to a bare metal application)? 

b) Assuming that the answer to the above question is yes - I need a counter that is consistent across all cores. I understand that reading CNTPCT_EL0 can be virtualized by the O/S. Are you confident that such reads are not virtualized in the case of PetaLinux and are thus consistent across the cores?

Thanks,

Beni

joe306
Scholar
Scholar
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Registered: ‎12-07-2018

Hello, am not using an OS, only bare-metal. Maybe I start a new discussion.

 

Thank you

Joe

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