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ldj
Contributor
Contributor
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Registered: ‎06-07-2020

A question about DTS for video

Dear all,

I hope all are doing great.

I am developing ZU5EV's video with Petalinux2020.01.  I have a DTS program about video, as shown below:

amba_pl: amba_pl@0 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges ;

uart2: serial@a0001000 {
clock-names = "s_axi_aclk";
clocks = <&axi_lite_clk>;
compatible = "xlnx,xps-uartlite-1.00.a";
status = "disabled";
reg = <0x0 0xa0001000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
};

axi_vdma_0: dma@a0000000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axis_mm2s_aclk", "m_axi_s2mm_aclk", "s_axis_s2mm_aclk";
clocks = <&axi_lite_clk>, <&axi_lite_clk>, <&axi_lite_clk>, <&axi_lite_clk>, <&axi_lite_clk>;
compatible = "xlnx,axi-vdma-6.3", "xlnx,axi-vdma-1.00.a";
interrupt-names = "mm2s_introut", "s2mm_introut";
interrupt-parent = <&gic>;
interrupts = <0 92 4 0 91 4>;
reg = <0x0 0xa0000000 0x0 0x1000>;
xlnx,addrwidth = <0x24>;
xlnx,flush-fsync = <0x1>;
xlnx,num-fstores = <0x3>;

dma-channel@a0000000 {
compatible = "xlnx,axi-vdma-mm2s-channel";
interrupts = <0 92 4>;
xlnx,datawidth = <0x10>;
xlnx,device-id = <0x0>;
xlnx,genlock-mode ;
};

dma-channel@a0000030 {
compatible = "xlnx,axi-vdma-s2mm-channel";
interrupts = <0 91 4>;
xlnx,datawidth = <0x30>;
xlnx,device-id = <0x0>;
xlnx,genlock-mode ;
};
};

axi_lite_clk: axi_lite_clk {
#clock-cells = <0>;
clock-frequency = <299997000>;
compatible = "fixed-clock";
};

vcap {
compatible = "xlnx,video";
xlnx,num-fstores = <0x3>;
dmas = <&axi_vdma_0 1>,
<&axi_vdma_0 0>;
dma-names = "port0", "port1";

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <1>;
direction = "output";
vput_out: endpoint {
remote-endpoint = <&tpg_in>;
};

};

port@1 {
reg = <0>;
direction = "input";
vcap_in: endpoint {
remote-endpoint = <&tpg_out>;
};

};
};
};

v_tpg_0 {
compatible = "xlnx,v-tpg-7.0";
xlnx,s-axi-ctrl-addr-width = <0x8>;
xlnx,s-axi-ctrl-data-width = <0x20>;
clocks = <&axi_lite_clk>;
reg = <0x0 0xa0010000 0x0 0x10000>;
reset-gpios = <&gpio 83 1>;

ports {
#address-cells = <1>;
#size-cells = <0>;

port@0 {
reg = <0>;
/*xlnx,video-format = <XVIP_VF_RBG>;*/
xlnx,video-width = <8>;
tpg_out: endpoint {
remote-endpoint = <&vcap_in>;
};
};

port@1 {
reg = <0>;
/*xlnx,video-format = <XVIP_VF_RBG>;*/
xlnx,video-width = <8>;
tpg_in: endpoint {
remote-endpoint = <&vput_out>;
};
};
};
};

};

When I added it to system-user.dtsi, the following error occurred after compilation:

ERROR: device-tree-xilinx-v2020.1+gitAUTOINC+bc84458333-r0 do_compile: Error executing a python function in exec_python_func() autogenerated:

The stack trace of python calls that resulted in this exception/failure was:
File: 'exec_python_func() autogenerated', lineno: 2, function: <module>
0001:
*** 0002:devicetree_do_compile(d)
0003:
File: '/home/ldj/work/5ev_myir/kvm/components/yocto/layers/core/meta/classes/devicetree.bbclass', lineno: 131, function: devicetree_do_compile
0127: if not(os.path.isfile(dtspath)) or not(dts.endswith(".dts") or devicetree_source_is_overlay(dtspath)):
0128: continue # skip non-.dts files and non-overlay files
0129: except:
0130: continue # skip if can't determine if overlay
*** 0131: devicetree_compile(dtspath, includes, d)
0132:}
0133:
0134:devicetree_do_install() {
0135: for DTB_FILE in `ls *.dtb *.dtbo`; do
File: '/home/ldj/work/5ev_myir/kvm/components/yocto/layers/core/meta/classes/devicetree.bbclass', lineno: 119, function: devicetree_compile
0115: dtcargs += ["-i", i]
0116: dtcargs += ["-o", "{0}.{1}".format(dtname, "dtbo" if isoverlay else "dtb")]
0117: dtcargs += ["-I", "dts", "-O", "dtb", "{0}.pp".format(dts)]
0118: bb.note("Running {0}".format(" ".join(dtcargs)))
*** 0119: subprocess.run(dtcargs, check = True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
0120:
0121:python devicetree_do_compile() {
0122: includes = expand_includes("DT_INCLUDE", d)
0123: listpath = d.getVar("DT_FILES_PATH")
File: '/home/ldj/petalinux/components/yocto/buildtools/sysroots/x86_64-petalinux-linux/usr/lib/python3.7/subprocess.py', lineno: 512, function: run
0508: raise
0509: retcode = process.poll()
0510: if check and retcode:
0511: raise CalledProcessError(retcode, process.args,
*** 0512: output=stdout, stderr=stderr)
0513: return CompletedProcess(process.args, retcode, stdout, stderr)
0514:
0515:
0516:def list2cmdline(seq):
Exception: subprocess.CalledProcessError: Command '['dtc', '-@', '-@', '-p', '0x1000', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/socionext', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/synaptics', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/broadcom', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/actions', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/ti', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/al', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/qcom', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/apm', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/zte', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/realtek', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/marvell', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/altera', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/sprd', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/rockchip', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/hisilicon', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/amlogic', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work/zynqmp_generic-xilinx-linux/device-tree/xilinx-v2020.1+gitAUTOINC+bc84458333-r0', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/bitmain', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/allwinner', '-i', '/home/ldj/work/5ev_myir/kvm/project-spec/configs/../../components/plnx_workspace/device-tree/device-tree', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/lg', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/mediatek', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/xilinx', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/renesas', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/exynos', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/arm', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/freescale', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/intel', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/cavium', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/include', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/nvidia', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/arch/arm64/boot/dts/amd', '-i', '/home/ldj/work/5ev_myir/kvm/build/tmp/work-shared/zynqmp-generic/kernel-source/scripts/dtc/include-prefixes', '-o', 'system-top.dtb', '-I', 'dts', '-O', 'dtb', 'system-top.dts.pp']' returned non-zero exit status 1.

Subprocess output:
Error: /home/ldj/work/5ev_myir/kvm/build/tmp/work/zynqmp_generic-xilinx-linux/device-tree/xilinx-v2020.1+gitAUTOINC+bc84458333-r0/system-user.dtsi:130.27-28 syntax error
FATAL ERROR: Unable to parse input tree

ERROR: Logfile of failure stored in: /home/ldj/work/5ev_myir/kvm/build/tmp/work/zynqmp_generic-xilinx-linux/device-tree/xilinx-v2020.1+gitAUTOINC+bc84458333-r0/temp/log.do_compile.86746
ERROR: Task (/home/ldj/work/5ev_myir/kvm/components/yocto/layers/meta-xilinx/meta-xilinx-bsp/recipes-bsp/device-tree/device-tree.bb:do_compile) failed with exit code '1'
NOTE: Tasks Summary: Attempted 2032 tasks of which 2025 didn't need to be rerun and 1 failed.

 

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4 Replies
stephenm
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Registered: ‎09-12-2007

The error is given below:

Subprocess output:
Error: /home/ldj/work/5ev_myir/kvm/build/tmp/work/zynqmp_generic-xilinx-linux/device-tree/xilinx-v2020.1+gitAUTOINC+bc84458333-r0/system-user.dtsi:130.27-28 syntax error
FATAL ERROR: Unable to parse input tree

 

If you open the system-user.dtsi, and go to line 130:

port@0 {
reg = <0>;
xlnx,video-format = <XVIP_VF_RBG>;
xlnx,video-width = <8>;
tpg_out: endpoint {
remote-endpoint = <&vcap_in>;
};
};

 

This should be a label. for example, &XVIP_VF_RBG. Same on Line 139. 

Also, if you are making changes to your DT, then you should isolate the DT from Yocto/Petalinx as this makes it alot easier to 

modify, compile, debug, ect..

 

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/341082130/Quick+guide+to+Debugging+Device+Tree+Generator+Issues

Also, it seems that you are using devicetree overlays, and re-using alot nodes in the system-user.dtsi and the pl.dtsi. You will likely see 

more issues here. I would recommend to try to get this to compile without the DTO first

 

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sarah77wicker
Contributor
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Registered: ‎11-05-2018

hi ldj,

the first thing i can see is that you're missing '&' in front of your declaration of v_tpg_0 in the system-user.dtsi

i guess you want to add the port configuration to the default tpg configuration generated in pl.dtsi.

in this case you have to link it as such :

&surname_device{
    /* your configuration*/
};

also no need to write it inside amba_pl since it has already been generated by the petalinux tools before. youre just adding parameter/configuration to an already made node

*if not* you need to do like you did for vdma or uart and give the address at the declaration:

tpg@xxxxxxxx{
    /*your config*/
};

 

second you're giving a remote point "vput_out" to the tpg that i couldnt find in the system-dtsi and pl.dtsi that you shared... i dont know if you defined it else where but this might cause you some issue as well.

hope this can help you for the debug

best regards,

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shabbirk
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Registered: ‎12-04-2016

Hi @ldj 

It looks the line 130 of your system-user.dtsi doesn't have proper syntax. Example adding xlnx,video-format here:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/80707675/Mem+2+Mem+VPSS-CSC+VPSS-SC+device

 

Best Regards

Shabbir

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ldj
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Registered: ‎06-07-2020

hi,stephenm

    Thank you very much for your reply,I solved my problem by turning off the FPGA Manager in Petalinux. and I can see the media0, Video0, and Video1 nodes in the dev directory

    I found that the pl. Dtsi file generated is different when the FPGA Manager is turned on or off.The details are as follows:

    

  • Open FPGA Manager:
  • /*
    * CAUTION: This file is automatically generated by Xilinx.
    * Version:
    * Today is: Mon Oct 26 02:41:36 2020
    */


    /dts-v1/;
    /plugin/;
    / {
    fragment@0 {
    target = <&fpga_full>;
    overlay0: __overlay__ {
    #address-cells = <2>;
    #size-cells = <2>;
    firmware-name = "top.bit.bin";
    resets = <&zynqmp_reset 116>;
    };
    };
    fragment@1 {
    target = <&amba>;
    overlay1: __overlay__ {
    afi0: afi0 {
    compatible = "xlnx,afi-fpga";
    config-afi = < 0 2>, <1 2>, <2 2>, 2>, <4 0>, <5 0>, <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <11 0>, <12 0>, <13 0>, <14 0x800>, <15 0x000>;
    };
    clocking0: clocking0 {
    #clock-cells = <0>;
    assigned-clock-rates = <99999001>;
    assigned-clocks = <&zynqmp_clk 71>;
    clock-output-names = "fabric_clk";
    clocks = <&zynqmp_clk 71>;
    compatible = "xlnx,fclk";
    };
    };
    };
    fragment@2 {
    target = <&amba>;
    overlay2: __overlay__ {
    #address-cells = <2>;
    #size-cells = <2>;
    axi_uartlite_0: serial@a0001000 {
    clock-names = "s_axi_aclk";
    clocks = <&misc_clk_0>;
    compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a";
    current-speed = <115200>;
    device_type = "serial";
    interrupt-names = "interrupt";
    interrupt-parent = <&gic>;
    interrupts = <0 89 1>;
    port-number = <1>;
    reg = <0x0 0xa0001000 0x0 0x1000>;
    xlnx,baudrate = <0x1c200>;
    xlnx,data-bits = <0x8>;
    xlnx,odd-parity = <0x0>;
    xlnx,s-axi-aclk-freq-hz-d = "299.997";
    xlnx,use-parity = <0x0>;
    };
    misc_clk_0: misc_clk_0 {
    #clock-cells = <0>;
    clock-frequency = <299997000>;
    compatible = "fixed-clock";
    };
    axi_vdma_0: dma@a0000000 {
    #dma-cells = <1>;
    clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axis_mm2s_aclk", "m_axi_s2mm_aclk", "s_axis_s2mm_aclk";
    clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>;
    compatible = "xlnx,axi-vdma-6.3", "xlnx,axi-vdma-1.00.a";
    interrupt-names = "mm2s_introut", "s2mm_introut";
    interrupt-parent = <&gic>;
    interrupts = <0 92 4 0 91 4>;
    reg = <0x0 0xa0000000 0x0 0x1000>;
    xlnx,addrwidth = <0x24>;
    xlnx,flush-fsync = <0x1>;
    xlnx,num-fstores = <0x3>;
    dma-channel@a0000000 {
    compatible = "xlnx,axi-vdma-mm2s-channel";
    interrupts = <0 92 4>;
    xlnx,datawidth = <0x10>;
    xlnx,device-id = <0x0>;
    xlnx,genlock-mode ;
    };
    dma-channel@a0000030 {
    compatible = "xlnx,axi-vdma-s2mm-channel";
    interrupts = <0 91 4>;
    xlnx,datawidth = <0x30>;
    xlnx,device-id = <0x0>;
    xlnx,genlock-mode ;
    };
    };
    v_tpg_0: v_tpg@a0010000 {
    clock-names = "ap_clk";
    clocks = <&misc_clk_0>;
    compatible = "xlnx,v-tpg-8.0", "xlnx,v-tpg-7.0";
    reg = <0x0 0xa0010000 0x0 0x10000>;
    xlnx,max-height = <2160>;
    xlnx,max-width = <4096>;
    xlnx,ppc = <1>;
    xlnx,s-axi-ctrl-addr-width = <8>;
    xlnx,s-axi-ctrl-data-width = <32>;
    };
    };
    };
    };

  • Close FPGA Manager:
  • /*
    * CAUTION: This file is automatically generated by Xilinx.
    * Version:
    * Today is: Mon Oct 26 11:38:39 2020
    */


    / {
    amba_pl: amba_pl@0 {
    #address-cells = <2>;
    #size-cells = <2>;
    compatible = "simple-bus";
    ranges ;
    axi_uartlite_0: serial@a0001000 {
    clock-names = "s_axi_aclk";
    clocks = <&misc_clk_0>;
    compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a";
    current-speed = <115200>;
    device_type = "serial";
    interrupt-names = "interrupt";
    interrupt-parent = <&gic>;
    interrupts = <0 89 1>;
    port-number = <1>;
    reg = <0x0 0xa0001000 0x0 0x1000>;
    xlnx,baudrate = <0x1c200>;
    xlnx,data-bits = <0x8>;
    xlnx,odd-parity = <0x0>;
    xlnx,s-axi-aclk-freq-hz-d = "299.997";
    xlnx,use-parity = <0x0>;
    };
    misc_clk_0: misc_clk_0 {
    #clock-cells = <0>;
    clock-frequency = <299997000>;
    compatible = "fixed-clock";
    };
    axi_vdma_0: dma@a0000000 {
    #dma-cells = <1>;
    clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axis_mm2s_aclk", "m_axi_s2mm_aclk", "s_axis_s2mm_aclk";
    clocks = <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>, <&misc_clk_0>;
    compatible = "xlnx,axi-vdma-6.3", "xlnx,axi-vdma-1.00.a";
    interrupt-names = "mm2s_introut", "s2mm_introut";
    interrupt-parent = <&gic>;
    interrupts = <0 92 4 0 91 4>;
    reg = <0x0 0xa0000000 0x0 0x1000>;
    xlnx,addrwidth = <0x24>;
    xlnx,flush-fsync = <0x1>;
    xlnx,num-fstores = <0x3>;
    dma-channel@a0000000 {
    compatible = "xlnx,axi-vdma-mm2s-channel";
    interrupts = <0 92 4>;
    xlnx,datawidth = <0x10>;
    xlnx,device-id = <0x0>;
    xlnx,genlock-mode ;
    };
    dma-channel@a0000030 {
    compatible = "xlnx,axi-vdma-s2mm-channel";
    interrupts = <0 91 4>;
    xlnx,datawidth = <0x30>;
    xlnx,device-id = <0x0>;
    xlnx,genlock-mode ;
    };
    };
    v_tpg_0: v_tpg@a0010000 {
    clock-names = "ap_clk";
    clocks = <&misc_clk_0>;
    compatible = "xlnx,v-tpg-8.0", "xlnx,v-tpg-7.0";
    reg = <0x0 0xa0010000 0x0 0x10000>;
    xlnx,max-height = <2160>;
    xlnx,max-width = <4096>;
    xlnx,ppc = <1>;
    xlnx,s-axi-ctrl-addr-width = <8>;
    xlnx,s-axi-ctrl-data-width = <32>;
    };
    };
    };

    

  • Do you have any information about it? If I want to configure the video driver while opening the FPGA Manager, how do I configure the device tree?

 

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