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Visitor aantonie
Visitor
470 Views
Registered: ‎10-30-2018

AXI DMA test error on zynqmp with fpga manager

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Hi all,

I'm working with custom board similar to zcu102 and i'm using vivado 2018.2 with petalinux 2019.1.

I'm trying to build simple axidma petalinux system with axidmatest module but i have problems  when i'm trying to use also fpga-manager.

After modprobe axidmatest there is a lot of errors:

root@test:~# modprobe axidmatest
[ 82.986030] dmatest: Started 1 threads using dma16chan0 dma16chan1 [ 83.254873] dma16chan0-dma1: dstbuf[0x4d] not copied! Expected c2, got 32 [ 83.261656] dma16chan0-dma1: dstbuf[0x4e] not copied! Expected c1, got 31 [ 83.006386] dma16chan0-dma1: srcbuf[0x95a] overwritten! Expected c5, got 35
[ 83.013348] dma16chan0-dma1: srcbuf[0x95b] overwritten! Expected c4, got 34
----
---- ---- [ 85.317913] src_off=0x1f08 dst_off=0x27e0 len=0x1530 [ 85.327846] dma16chan0-dma1: terminating after 5 tests, 5 failures (status 0)

Below there is block design, zynq ps-pl configuration, axidma ip configuration and address editor.

axi_dma_top.pngaxi_dma_zynq_conf.png

axidma_address.png

axi_dma_conf.png

System-user.dtsi (fpga-manager enabled):

/include/ "system-conf.dtsi"
/ {
	axidmatest_0: axidmatest@0 {
		compatible ="xlnx,axi-dma-test-1.00.a";
	};
};

and pl.dtsi

/dts-v1/;
/plugin/;
/ {
	fragment@0 {
		target = <&fpga_full>;
		overlay0: __overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;
			firmware-name = "dma_test_wrapper.bit.bin";
			resets = <&zynqmp_reset 116>;
		};
	};
	fragment@1 {
		target = <&amba>;
		overlay1: __overlay__ {
			afi0: afi0 {
				compatible = "xlnx,afi-fpga";
				config-afi = < 0 1>, <1 1>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <11 0>, <12 0>, <13 0>, <14 0xa00>, <15 0x000>;
			};
			clocking0: clocking0 {
				#clock-cells = <0>;
				assigned-clock-rates = <99999000>;
				assigned-clocks = <&zynqmp_clk 71>;
				clock-output-names = "fabric_clk";
				clocks = <&zynqmp_clk 71>;
				compatible = "xlnx,fclk";
			};
		};
	};
	fragment@2 {
		target = <&amba>;
		overlay2: __overlay__ {
			#address-cells = <2>;
			#size-cells = <2>;
			axi_dma_0: dma@a0000000 {
				#dma-cells = <1>;
				clock-names = "s_axi_lite_aclk", "m_axi_sg_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
				clocks = <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
				compatible = "xlnx,axi-dma-7.1", "xlnx,axi-dma-1.00.a";
				interrupt-names = "mm2s_introut", "s2mm_introut";
				interrupt-parent = <&gic>;
				interrupts = <0 89 4 0 90 4>;
				reg = <0x0 0xa0000000 0x0 0x1000>;
				xlnx,addrwidth = <0x40>;
				xlnx,include-sg ;
				xlnx,sg-length-width = <0x17>;
				dma-channel@a0000000 {
					compatible = "xlnx,axi-dma-mm2s-channel";
					dma-channels = <0x1>;
					interrupts = <0 89 4>;
					xlnx,datawidth = <0x40>;
					xlnx,device-id = <0x0>;
				};
				dma-channel@a0000030 {
					compatible = "xlnx,axi-dma-s2mm-channel";
					dma-channels = <0x1>;
					interrupts = <0 90 4>;
					xlnx,datawidth = <0x40>;
					xlnx,device-id = <0x0>;
				};
			};
			psu_ctrl_ipi: PERIPHERAL@ff380000 {
				compatible = "xlnx,PERIPHERAL-1.0";
				reg = <0x0 0xff380000 0x0 0x80000>;
			};
			psu_message_buffers: PERIPHERAL@ff990000 {
				compatible = "xlnx,PERIPHERAL-1.0";
				reg = <0x0 0xff990000 0x0 0x10000>;
			};
		};
	};

	fragment@3 {
		target = <&axidmatest_0>;
		overlay3: __overlay__ {
				compatible ="xlnx,axi-dma-test-1.00.a";
				dmas = <&axi_dma_0 0
					&axi_dma_0 1>;
				dma-names = "axidma0", "axidma1";
		};
	};
};

In petalinux using overlays i have successfully program fpga:

mkdir /configfs
mount -t configfs configfs /configfs
cd /configfs/device-tree/overlays/
echo 0 > /sys/class/fpga_manager/fpga0/flags 
cp /run/media/mmcblk1p1/dma_test_wrapper.bit.bin /lib/firmware/
cp /run/media/mmcblk1p1/pl.dtbo /lib/firmware/
mkdir full
echo -n "pl.dtbo" > full/path

and everything looks fine

fpga_manager fpga0: writing dma_test_wrapper.bit.bin to Xilinx ZynqMP FPGA Manager
xilinx-vdma a0000000.dma: Xilinx AXI DMA Engine Driver Probed!!

but after inserting axidmatest module i there is a lot of errors:

root@test:~# modprobe axidmatest
[ 82.986030] dmatest: Started 1 threads using dma16chan0 dma16chan1 [ 82.992471] dma16chan0-dma1: srcbuf[0x958] overwritten! Expected c7, got 37 [ 82.999433] dma16chan0-dma1: srcbuf[0x959] overwritten! Expected c6, got 36 [ 83.006386] dma16chan0-dma1: srcbuf[0x95a] overwritten! Expected c5, got 35 [ 83.013348] dma16chan0-dma1: srcbuf[0x95b] overwritten! Expected c4, got 34 [ 83.020304] dma16chan0-dma1: srcbuf[0x95c] overwritten! Expected c3, got 33 [ 83.027259] dma16chan0-dma1: srcbuf[0x95d] overwritten! Expected c2, got 32 [ 83.034212] dma16chan0-dma1: srcbuf[0x95e] overwritten! Expected c1, got 31 [ 83.041164] dma16chan0-dma1: srcbuf[0x95f] overwritten! Expected c0, got 30 [ 83.048117] dma16chan0-dma1: srcbuf[0x960] overwritten! Expected df, got 2f [ 83.055069] dma16chan0-dma1: srcbuf[0x961] overwritten! Expected de, got 2e [ 83.062023] dma16chan0-dma1: srcbuf[0x962] overwritten! Expected dd, got 2d [ 83.068976] dma16chan0-dma1: srcbuf[0x963] overwritten! Expected dc, got 2c [ 83.075928] dma16chan0-dma1: srcbuf[0x964] overwritten! Expected db, got 2b [ 83.082880] dma16chan0-dma1: srcbuf[0x965] overwritten! Expected da, got 2a [ 83.089834] dma16chan0-dma1: srcbuf[0x966] overwritten! Expected d9, got 29 [ 83.096785] dma16chan0-dma1: srcbuf[0x967] overwritten! Expected d8, got 28 [ 83.103739] dma16chan0-dma1: srcbuf[0x968] overwritten! Expected d7, got 27 [ 83.110691] dma16chan0-dma1: srcbuf[0x969] overwritten! Expected d6, got 26 [ 83.117645] dma16chan0-dma1: srcbuf[0x96a] overwritten! Expected d5, got 25 [ 83.124599] dma16chan0-dma1: srcbuf[0x96b] overwritten! Expected d4, got 24 [ 83.131551] dma16chan0-dma1: srcbuf[0x96c] overwritten! Expected d3, got 23 [ 83.138511] dma16chan0-dma1: srcbuf[0x96d] overwritten! Expected d2, got 22 [ 83.145465] dma16chan0-dma1: srcbuf[0x96e] overwritten! Expected d1, got 21 [ 83.152416] dma16chan0-dma1: srcbuf[0x96f] overwritten! Expected d0, got 20 [ 83.159370] dma16chan0-dma1: srcbuf[0x970] overwritten! Expected cf, got 3f [ 83.166322] dma16chan0-dma1: srcbuf[0x971] overwritten! Expected ce, got 3e [ 83.173276] dma16chan0-dma1: srcbuf[0x972] overwritten! Expected cd, got 3d [ 83.180227] dma16chan0-dma1: srcbuf[0x973] overwritten! Expected cc, got 3c [ 83.187181] dma16chan0-dma1: srcbuf[0x974] overwritten! Expected cb, got 3b [ 83.194133] dma16chan0-dma1: srcbuf[0x975] overwritten! Expected ca, got 3a [ 83.201087] dma16chan0-dma1: srcbuf[0x976] overwritten! Expected c9, got 39 [ 83.208038] dma16chan0-dma1: srcbuf[0x977] overwritten! Expected c8, got 38 [ 83.215795] dma16chan0-dma1: 136632 errors suppressed [ 83.220966] dma16chan0-dma1: dstbuf[0x48] not copied! Expected c7, got 37 [ 83.227744] dma16chan0-dma1: dstbuf[0x49] not copied! Expected c6, got 36 [ 83.234530] dma16chan0-dma1: dstbuf[0x4a] not copied! Expected c5, got 35 [ 83.241310] dma16chan0-dma1: dstbuf[0x4b] not copied! Expected c4, got 34 [ 83.248088] dma16chan0-dma1: dstbuf[0x4c] not copied! Expected c3, got 33 [ 83.254873] dma16chan0-dma1: dstbuf[0x4d] not copied! Expected c2, got 32 [ 83.261656] dma16chan0-dma1: dstbuf[0x4e] not copied! Expected c1, got 31 [ 83.268435] dma16chan0-dma1: dstbuf[0x4f] not copied! Expected c0, got 30 [ 83.275214] dma16chan0-dma1: dstbuf[0x50] not copied! Expected df, got 2f [ 83.281994] dma16chan0-dma1: dstbuf[0x51] not copied! Expected de, got 2e [ 83.288772] dma16chan0-dma1: dstbuf[0x52] not copied! Expected dd, got 2d [ 83.295552] dma16chan0-dma1: dstbuf[0x53] not copied! Expected dc, got 2c [ 83.302330] dma16chan0-dma1: dstbuf[0x54] not copied! Expected db, got 2b [ 83.309110] dma16chan0-dma1: dstbuf[0x55] not copied! Expected da, got 2a [ 83.315888] dma16chan0-dma1: dstbuf[0x56] not copied! Expected d9, got 29 [ 83.322668] dma16chan0-dma1: dstbuf[0x57] not copied! Expected d8, got 28 [ 83.329447] dma16chan0-dma1: dstbuf[0x58] not copied! Expected d7, got 27 [ 83.336227] dma16chan0-dma1: dstbuf[0x59] not copied! Expected d6, got 26 [ 83.343005] dma16chan0-dma1: dstbuf[0x5a] not copied! Expected d5, got 25 [ 83.349785] dma16chan0-dma1: dstbuf[0x5b] not copied! Expected d4, got 24 [ 83.356563] dma16chan0-dma1: dstbuf[0x5c] not copied! Expected d3, got 23 [ 83.363343] dma16chan0-dma1: dstbuf[0x5d] not copied! Expected d2, got 22 [ 83.370121] dma16chan0-dma1: dstbuf[0x5e] not copied! Expected d1, got 21 [ 83.376902] dma16chan0-dma1: dstbuf[0x5f] not copied! Expected d0, got 20 [ 83.383682] dma16chan0-dma1: dstbuf[0x60] not copied! Expected cf, got 3f [ 83.390460] dma16chan0-dma1: dstbuf[0x61] not copied! Expected ce, got 3e [ 83.397238] dma16chan0-dma1: dstbuf[0x62] not copied! Expected cd, got 3d [ 83.404018] dma16chan0-dma1: dstbuf[0x63] not copied! Expected cc, got 3c [ 83.410796] dma16chan0-dma1: dstbuf[0x64] not copied! Expected cb, got 3b [ 83.417577] dma16chan0-dma1: dstbuf[0x65] not copied! Expected ca, got 3a [ 83.424355] dma16chan0-dma1: dstbuf[0x66] not copied! Expected c9, got 39 [ 83.431135] dma16chan0-dma1: dstbuf[0x67] not copied! Expected c8, got 38 [ 83.438719] dma16chan0-dma1: 136632 errors suppressed [ 83.444051] dma16chan0-dma1: #0: 273328 errors with [ 83.444055] src_off=0x958 dst_off=0x48 len=0x3088 ---- [ 85.317913] src_off=0x1f08 dst_off=0x27e0 len=0x1530 [ 85.327846] dma16chan0-dma1: terminating after 5 tests, 5 failures (status 0)

I have done test without fpga-manager and everything works fine.

system-user.dtsi without fpga-manager:

/include/ "system-conf.dtsi"
/ {
	axidmatest_0: axidmatest@0 {
		compatible ="xlnx,axi-dma-test-1.00.a";
		dmas = <&axi_dma_0 0
			&axi_dma_0 1>;
		dma-names = "axidma0", "axidma1";
	};
};

and axidmatest is working:

root@test:~# modprobe axidmatest
[   28.432545] dmatest: Started 1 threads using dma0chan0 dma0chan1
[   28.456685] dma0chan0-dma0c: terminating after 5 tests, 0 failures (status 0)

Does anyone known why axidmatest fails in system with fpga-manager enabled? Without fpga-manager everything is ok. Any ideas?

 

1 Solution

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Highlighted
Xilinx Employee
Xilinx Employee
213 Views
Registered: ‎02-20-2014

Re: AXI DMA test error on zynqmp with fpga manager

Jump to solution

It seems the issue is related to overlay DT runtime ordering. Xilinx dma driver [1] assumes MM2S channel node is probed first.
But when fpga manager is enabled this channel load order is changed and s2mm channel is probed first.

In dmatest client [2] we provide a mapping. It works when MM2S channel is probed first so 0 is for TX. 

But this assumption breaks when S2MM channel is probed first.

  • dmas: a list of <[DMA device phandle] [Channel ID]> pairs, where Channel ID is '0' for write/tx and '1' for read/rx channel.

Possible solution:
a) As a quick workaround in DTS we can swap the channel-id in dmas node. dmas = <&axi_dma_0 1 &axi_dma_0 0>;
Or we can modify axidmatest client driver and in dma_request_slave_channel change axidma0 -> axidma1 and vice-versa.
b) I am exploring on how we can fix this DT ordering dependency in a generic way and will send out an update.

[1] : DT node
axidma {
<snip>
dma-channel@a0000000

{ compatible = "xlnx,axi-dma-mm2s-channel"; dma-channels = <0x1>; interrupts = <0 89 4>; xlnx,datawidth = <0x20>; xlnx,device-id = <0x0>; }

;
dma-channel@a0000030

{ compatible = "xlnx,axi-dma-s2mm-channel"; dma-channels = <0x1>; interrupts = <0 90 4>; xlnx,datawidth = <0x20>; xlnx,device-id = <0x0>; }

;
}

[2] :
axidmatest_1: axidmatest@1

{ compatible ="xlnx,axi-dma-test-1.00.a"; dmas = <&axi_dma_0 0 &axi_dma_0 1>; dma-names = "axidma0", "axidma1"; }

;

View solution in original post

2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
214 Views
Registered: ‎02-20-2014

Re: AXI DMA test error on zynqmp with fpga manager

Jump to solution

It seems the issue is related to overlay DT runtime ordering. Xilinx dma driver [1] assumes MM2S channel node is probed first.
But when fpga manager is enabled this channel load order is changed and s2mm channel is probed first.

In dmatest client [2] we provide a mapping. It works when MM2S channel is probed first so 0 is for TX. 

But this assumption breaks when S2MM channel is probed first.

  • dmas: a list of <[DMA device phandle] [Channel ID]> pairs, where Channel ID is '0' for write/tx and '1' for read/rx channel.

Possible solution:
a) As a quick workaround in DTS we can swap the channel-id in dmas node. dmas = <&axi_dma_0 1 &axi_dma_0 0>;
Or we can modify axidmatest client driver and in dma_request_slave_channel change axidma0 -> axidma1 and vice-versa.
b) I am exploring on how we can fix this DT ordering dependency in a generic way and will send out an update.

[1] : DT node
axidma {
<snip>
dma-channel@a0000000

{ compatible = "xlnx,axi-dma-mm2s-channel"; dma-channels = <0x1>; interrupts = <0 89 4>; xlnx,datawidth = <0x20>; xlnx,device-id = <0x0>; }

;
dma-channel@a0000030

{ compatible = "xlnx,axi-dma-s2mm-channel"; dma-channels = <0x1>; interrupts = <0 90 4>; xlnx,datawidth = <0x20>; xlnx,device-id = <0x0>; }

;
}

[2] :
axidmatest_1: axidmatest@1

{ compatible ="xlnx,axi-dma-test-1.00.a"; dmas = <&axi_dma_0 0 &axi_dma_0 1>; dma-names = "axidma0", "axidma1"; }

;

View solution in original post

Visitor aantonie
Visitor
189 Views
Registered: ‎10-30-2018

Re: AXI DMA test error on zynqmp with fpga manager

Jump to solution

I have tested your workaround with swapped channels-id. 

Changes in pl.dtsi are marked below

	fragment@3 {
		target = <&axidmatest_0>;
		overlay3: __overlay__ {
				compatible ="xlnx,axi-dma-test-1.00.a";
				dmas = <&axi_dma_0 1
					&axi_dma_0 0>;
				dma-names = "axidma0", "axidma1";
		};
	};

And now it's working, so thank you for workaround.

Regards,

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