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Explorer
Explorer
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Registered: ‎03-22-2016

AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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I have an AXI DMA loopback set up as shown in the attached block diagram. I have tried several iterations on it to see if I was making a configuration mistake, but none of the changes I made had any impact.

 

Petalinux is a new project built from BSP, configured the kernel to build xilinx_dma and axidmatest as modules and enable DMA debug logging.

 

I also added project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi as follows:

 

 

/include/ "system-conf.dtsi"
/ {
    dmatest_0: dmatest@0 {
        compatible ="xlnx,axi-dma-test-1.00.a";
        dmas = <&axi_dma_0 0 &axi_dma_0 1>;
        dma-names = "axidma0", "axidma1";
    };
};

 

On boot, I see a proper initialization of the AXI DMA module:

 

 

[ 3.894698] xilinx-vdma a0000000.dma: Xilinx AXI DMA Engine Driver Probed!!


When I modprobe the axidmatest driver, however, I get the following errors:

 

 

root@xilinx-zcu102-zu9-es2-rev1_0-2017:~# modprobe axidmatest iterations=1
[ 906.006849] dmatest: Started 1 threads using dma16chan0 dma16chan1
[ 906.008873] dma16chan0-dma1: verifying source buffer...
[ 906.010233] dma16chan0-dma1: verifying dest buffer...
[ 906.010237] dma16chan0-dma1: dstbuf[0x0] mismatch! Expected 1f, got 00
[ 906.010239] dma16chan0-dma1: dstbuf[0x1] mismatch! Expected 1e, got 00
[ 906.010241] dma16chan0-dma1: dstbuf[0x2] mismatch! Expected 1d, got 00
[ 906.010243] dma16chan0-dma1: dstbuf[0x3] mismatch! Expected 1c, got 00
[ 906.010245] dma16chan0-dma1: dstbuf[0x4] mismatch! Expected 1b, got 00
[ 906.010247] dma16chan0-dma1: dstbuf[0x5] mismatch! Expected 1a, got 00
[ 906.010248] dma16chan0-dma1: dstbuf[0x6] mismatch! Expected 19, got 00
[ 906.010250] dma16chan0-dma1: dstbuf[0x7] mismatch! Expected 18, got 00
[ 906.010252] dma16chan0-dma1: dstbuf[0x8] mismatch! Expected 17, got 00
[ 906.010254] dma16chan0-dma1: dstbuf[0x9] mismatch! Expected 16, got 00
[ 906.010256] dma16chan0-dma1: dstbuf[0xa] mismatch! Expected 15, got 00
[ 906.010258] dma16chan0-dma1: dstbuf[0xb] mismatch! Expected 14, got 00
[ 906.010260] dma16chan0-dma1: dstbuf[0xc] mismatch! Expected 13, got 00
[ 906.010262] dma16chan0-dma1: dstbuf[0xd] mismatch! Expected 12, got 00
[ 906.010264] dma16chan0-dma1: dstbuf[0xe] mismatch! Expected 11, got 00
[ 906.010266] dma16chan0-dma1: dstbuf[0xf] mismatch! Expected 10, got 00
[ 906.010268] dma16chan0-dma1: dstbuf[0x10] mismatch! Expected 0f, got 00
[ 906.010270] dma16chan0-dma1: dstbuf[0x11] mismatch! Expected 0e, got 00
[ 906.010272] dma16chan0-dma1: dstbuf[0x12] mismatch! Expected 0d, got 00
[ 906.010274] dma16chan0-dma1: dstbuf[0x13] mismatch! Expected 0c, got 00
[ 906.010276] dma16chan0-dma1: dstbuf[0x14] mismatch! Expected 0b, got 00
[ 906.010278] dma16chan0-dma1: dstbuf[0x15] mismatch! Expected 0a, got 00
[ 906.010279] dma16chan0-dma1: dstbuf[0x16] mismatch! Expected 09, got 00
[ 906.010281] dma16chan0-dma1: dstbuf[0x17] mismatch! Expected 08, got 00
[ 906.010283] dma16chan0-dma1: dstbuf[0x18] mismatch! Expected 07, got 00
[ 906.010285] dma16chan0-dma1: dstbuf[0x19] mismatch! Expected 06, got 00
[ 906.010287] dma16chan0-dma1: dstbuf[0x1a] mismatch! Expected 05, got 00
[ 906.010289] dma16chan0-dma1: dstbuf[0x1b] mismatch! Expected 04, got 00
[ 906.010291] dma16chan0-dma1: dstbuf[0x1c] mismatch! Expected 03, got 00
[ 906.010293] dma16chan0-dma1: dstbuf[0x1d] mismatch! Expected 02, got 00
[ 906.010295] dma16chan0-dma1: dstbuf[0x1e] mismatch! Expected 01, got 00
[ 906.010297] dma16chan0-dma1: dstbuf[0x20] mismatch! Expected 1f, got 00
[ 906.010361] dma16chan0-dma1: 7008 errors suppressed
[ 906.011569] dma16chan0-dma1: dstbuf[0x3ba4] mismatch! Expected 1b, got 00
[ 906.011571] dma16chan0-dma1: dstbuf[0x3ba5] mismatch! Expected 1a, got 00
[ 906.011573] dma16chan0-dma1: dstbuf[0x3ba6] mismatch! Expected 19, got 00
[ 906.011575] dma16chan0-dma1: dstbuf[0x3ba7] mismatch! Expected 18, got 00
[ 906.011577] dma16chan0-dma1: dstbuf[0x3ba8] mismatch! Expected 17, got 00
[ 906.011579] dma16chan0-dma1: dstbuf[0x3ba9] mismatch! Expected 16, got 00
[ 906.011581] dma16chan0-dma1: dstbuf[0x3baa] mismatch! Expected 15, got 00
[ 906.011583] dma16chan0-dma1: dstbuf[0x3bab] mismatch! Expected 14, got 00
[ 906.011585] dma16chan0-dma1: dstbuf[0x3bac] mismatch! Expected 13, got 00
[ 906.011587] dma16chan0-dma1: dstbuf[0x3bad] mismatch! Expected 12, got 00
[ 906.011589] dma16chan0-dma1: dstbuf[0x3bae] mismatch! Expected 11, got 00
[ 906.011591] dma16chan0-dma1: dstbuf[0x3baf] mismatch! Expected 10, got 00
[ 906.011593] dma16chan0-dma1: dstbuf[0x3bb0] mismatch! Expected 0f, got 00
[ 906.011595] dma16chan0-dma1: dstbuf[0x3bb1] mismatch! Expected 0e, got 00
[ 906.011597] dma16chan0-dma1: dstbuf[0x3bb2] mismatch! Expected 0d, got 00
[ 906.011599] dma16chan0-dma1: dstbuf[0x3bb3] mismatch! Expected 0c, got 00
[ 906.011601] dma16chan0-dma1: dstbuf[0x3bb4] mismatch! Expected 0b, got 00
[ 906.011603] dma16chan0-dma1: dstbuf[0x3bb5] mismatch! Expected 0a, got 00
[ 906.011605] dma16chan0-dma1: dstbuf[0x3bb6] mismatch! Expected 09, got 00
[ 906.011607] dma16chan0-dma1: dstbuf[0x3bb7] mismatch! Expected 08, got 00
[ 906.011609] dma16chan0-dma1: dstbuf[0x3bb8] mismatch! Expected 07, got 00
[ 906.011610] dma16chan0-dma1: dstbuf[0x3bb9] mismatch! Expected 06, got 00
[ 906.011612] dma16chan0-dma1: dstbuf[0x3bba] mismatch! Expected 05, got 00
[ 906.011614] dma16chan0-dma1: dstbuf[0x3bbb] mismatch! Expected 04, got 00
[ 906.011616] dma16chan0-dma1: dstbuf[0x3bbc] mismatch! Expected 03, got 00
[ 906.011618] dma16chan0-dma1: dstbuf[0x3bbd] mismatch! Expected 02, got 00
[ 906.011620] dma16chan0-dma1: dstbuf[0x3bbe] mismatch! Expected 01, got 00
[ 906.011622] dma16chan0-dma1: dstbuf[0x3bc0] mismatch! Expected 1f, got 00
[ 906.011624] dma16chan0-dma1: dstbuf[0x3bc1] mismatch! Expected 1e, got 00
[ 906.011626] dma16chan0-dma1: dstbuf[0x3bc2] mismatch! Expected 1d, got 00
[ 906.011628] dma16chan0-dma1: dstbuf[0x3bc3] mismatch! Expected 1c, got 00
[ 906.011630] dma16chan0-dma1: dstbuf[0x3bc4] mismatch! Expected 1b, got 00
[ 906.011737] dma16chan0-dma1: 11859 errors suppressed
[ 906.011741] dma16chan0-dma1: #0: 18931 errors with
[ 906.011741] src_off=0x490 dst_off=0x294 len=0x3910
[ 906.011752] dma16chan0-dma1: terminating after 1 tests, 1 failures (status 0)

 

Any suggestions are welcome, especially if you have the same hardware and are able to verify what I am seeing (or find that it works for you!). Thanks!

 

block_design.png
memory_map.png
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
5,303 Views
Registered: ‎10-04-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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Hi @jeffsimpson@pharbanau, and @jackfrye11,

I was able to get this to work by enabling the AXI DMA to access memory above the 4GB boundary. A few steps are required to do this.

 

1. In the configuration window for your AXI DMA, set the address width to 64 bits. 

axiDMAConfig.JPG

2. Enable the "High Address" range for the Zynq US+ MPSoC. 

highAddress.JPG

3. Go to Address Editor. You will likely find the new address ranges under "Unmapped Slaves." Choose Auto-Assign and you should see HPC0_DDR_HIGH mapped into the address space for all of the AXI DMA master ports.

addrEd.JPG

 

Regards,

 

Deanna

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16 Replies
Explorer
Explorer
4,528 Views
Registered: ‎03-22-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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I was able to get AXI DMA to function in 2017.1 as follows:

- Same block design as shown above, but using AXI Interconnect blocks instead of SmartConnect blocks.

- Same Petalinux procedure, as before, but with some changes.

 

Change #1: The misc_clk_0 block is generated improperly in 2017.1 (empty clock definition), so it needs to be defined in  project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi:

/include/ "system-conf.dtsi"
/ {
    dmatest_0: dmatest@0 {
        compatible ="xlnx,axi-dma-test-1.00.a";
        dmas = <&axi_dma_0 0 &axi_dma_0 1>;
        dma-names = "axidma0", "axidma1";
    };
};

&misc_clk_0 {
    compatible = "fixed-clock";
    #clock-cells = <0>;
    clock-frequency = <100>;
};

 

Change #2: The AXI DMA test application has a bugfix that needs to be cherry-picked and applied to the 2017.1 linux-xlnx kernel release.

 

git clone https://github.com/Xilinx/linux-xlnx.git
cd linux-xlnx/
git checkout v2017.1
git cherry-pick a92614bf1b57cc3342fe0d0cc21df8390d587b6c

Then, use petalinux-config to set the kernel source to be that cloned copy.

 

Still trying to figure out what broke between 2017.1 and 2017.4, as I am still unable to get the AXI DMA to work in 2017.4 using nearly identical methods to 2017.1. Any help would be much appreciated.

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Participant pharbanau
Participant
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Registered: ‎12-20-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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Hi Jeff,

 

I have the same issue with axidmatest using Vivado 2017.4, and my test block design is identical to yours. Have you, probably, figured out what is wrong with 2017.4?

 

I'm downloading vivado and petalinux 2017.1 to try them, since as I understood you've succsessfully ran axidmatest using this version.

 

Pavel

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Explorer
Explorer
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Registered: ‎03-22-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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No, I haven't figured out the problem, yet. I'll certainly post when I have something!

 

I was able to get it to work with a microzed in 2017.4, which leads me to believe that the problem is specific to the ZCU102, or perhaps with all Zynq UltraScale+ devices.

 

That got me down the path of wondering if it has to do with the address or data width, so I'm iterating over a bunch of different configurations. I have noticed that I get different results, but I haven't found a successful configuration, yet.

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Explorer
Explorer
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Registered: ‎10-19-2017

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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You actually look like you did everything right. I have gotten the same design to work in 2017.3. I would suggest that when you create your PetaLinux project, you forgo adding the -s <bsp> and simply use the --template option and ensure that you feed it the hdf. That was the only difference between what you did and what I did. Perhaps there is not template in PetaLinux included for zcu102?

 

The default address widths worked for my scatter-gather (axidmatest) design in 2017.3

 

However, I have only worked with zc706.

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Explorer
Explorer
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Registered: ‎03-22-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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@jackfrye11 wrote:

You actually look like you did everything right. I have gotten the same design to work in 2017.3. I would suggest that when you create your PetaLinux project, you forgo adding the -s <bsp> and simply use the --template option and ensure that you feed it the hdf. That was the only difference between what you did and what I did. Perhaps there is not template in PetaLinux included for zcu102?

 

The default address widths worked for my scatter-gather (axidmatest) design in 2017.3

 

However, I have only worked with zc706.


That's both encouraging and discouraging. Good to know that I'm doing it right, bummer that it's not working on this board / version and there isn't some obvious box I'm forgetting to check that will make it work reliably. I was really working on getting AXI DMA set up in a way that makes it easy to use across multiple boards. As in, I'd get a new board on my desk, drop an AXI DMA in the design and have high speed data to the PL going in an hour. Given how difficult it is to get it working on one (and how fragile the combinations of vivado and kernel versions are), I don't think I can make the case that this should be done on other designs, yet.

 

Interesting idea to try a generic template. Xilinx does provide BSPs for that board (ZCU102 BSP) and they even include the specific hardware level I have (ES2). I'm feeding the hdf in anyway, so maybe it will still work?

I'm willing to blame the board for a lot of things, this has given us nothing but trouble. We had a couple power supplies fail right out of the gate, a lot of SD card corruption we didn't deserve, and this one can't seem to use the transceivers on the initial bootup and programming (but if you reprogram after boot it works fine).

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Explorer
Explorer
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Registered: ‎10-19-2017

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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I would think it would work better on a ZCU102, which is a Xilinx-distributed board than a MicroZed, which has its own bsps that are maintained outside of Xilinx. I would suggest filing an SR if you have the support. Considering you are working with new version of the software and a newer board, it may lead to a CR. The MPSoC has the latest Zynq and should work with the 2017.4.

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Participant pharbanau
Participant
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Registered: ‎12-20-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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Hi @jeffsimpson @jackfrye11

 

Thanks for your comments guys.

Actually I have tried to go with both options: creating project as zynqMP template and using -s <bsp>. Neither option worked for me, I still see that axidmatest fails.

BTW, I'm using production silicon, ZCU102 board revision 1.1.

 

I suspect that the issue is related to software cache management (or there might be some bug in Processing system IP). I posted some info in the last message here https://forums.xilinx.com/t5/AXI-Infrastructure/Ultrascale-AXI-DMA-loopback-test/td-p/830438.

I'm thinking now to modify axidmatest, not to use kmalloc -> dma_map_single for data buffers, but to allocate memory from CMA region using dma_alloc_coherent. May be this wll give different result..

 

Best,

Pavel

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Explorer
Explorer
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Registered: ‎03-22-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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I am starting to suspect a bug as well. I built identical designs for 2017.1 and 2017.4. Works in 2017.1, doesn't work in 2017.4. I then started pulling things from 2017.1 into 2017.4. The device tree modifications, the kernel (incl xilinx_dma and axidmatest).

It would be great if somebody from Xilinx could just confirm what we're seeing, even if there isn't a fix, yet.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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Hi Everyone,

I am seeing the same issue in 2017.4 and am opening a bug with the developers.

 

Regards,

 

Deanna

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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Hi @jeffsimpson@pharbanau, and @jackfrye11,

I was able to get this to work by enabling the AXI DMA to access memory above the 4GB boundary. A few steps are required to do this.

 

1. In the configuration window for your AXI DMA, set the address width to 64 bits. 

axiDMAConfig.JPG

2. Enable the "High Address" range for the Zynq US+ MPSoC. 

highAddress.JPG

3. Go to Address Editor. You will likely find the new address ranges under "Unmapped Slaves." Choose Auto-Assign and you should see HPC0_DDR_HIGH mapped into the address space for all of the AXI DMA master ports.

addrEd.JPG

 

Regards,

 

Deanna

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Explorer
Explorer
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Registered: ‎03-22-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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Worked perfectly! Enabling "High Address" was exactly what I was missing. Thanks so much.

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Participant pharbanau
Participant
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Registered: ‎12-20-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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Hi Deanna,

 

It works for me as well. I've used HP1 port and enabled High-Address as you advised. Thanks a lot!

 

Pavel

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Explorer
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Registered: ‎05-22-2008

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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@jeffsimpson

 

Do you know from where misc_clk0 comes? I see it in my devicetree, but my HW design doesn't have this clock. I also don't see nodes in my pl device tree for my pl clocks. The freq from one of my pl clocks in that which is specified in the misc_clk0 devicetree entry, but I can't find where that sort of translation may have occurred.

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Contributor
Contributor
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Registered: ‎05-03-2018

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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how to solve this issue on zynq 7000
Regards,
majic
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Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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@jeffsimpson @demarco thank you for your post and answers.

I think we ran into the same issue, I built a Zynq US+ design with a DMA in loopback, I started from the block design on the Xilinx wiki page 'Linux DMA from user space', but I replaced the AXI Interconnect with an AXI Smartconnect, as Xilinx seems to recommend this everywhere (however by default the design assistant still instantiates an AXI Interconnect, kinda strange).

I was unsure about the consequences of replacing the interconnect with a smarconnect IP, hence I posted that question here : Use AXI SmartConnect instead of AXI Interconnect on wiki 'Linux DMA from user space'

So @demarco  I can see you replaced AXI SmartConnects by AXI Interconnects ... is that key to the solution, or would this also work with SmartConnects? Or do these not support 64-bit addressing?

** kudo if the answer was helpful. Accept as solution if your question is answered **
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Re: AXI DMA test error, zcu102 ES2 Petalinux 2017.4

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Hi @ronnywebers,

I will follow up on your question on the new thread since it is a different issue than this thread tackles.

Regards,

Deanna

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