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Observer qswsjs
Registered: ‎07-18-2013

AXI DMA7.1 Cyclic mode problem


I'm using a reference design that includes an Analog to Digital Converter (ADC) connected to the FMC connector,AXI DMAand DDR3 Ram on.I want transfer the  data from AD to DDR via AXI DMA continuously.


Now I use ISE 14.7,the lastest vertion of AXI DMA is 6.03a,it doesn't support cyclic BD mode .I know the lastest vertion of DMA in VIVADO is 7.1,it support cyclic BD mode. So I copy the VIVADO'S DMA IP(v7.1) to ISE14.7, I use it in xps like blow my attachment.


1)、The first question, can I copy he vivado's DMA IP(v7.1) to ISE14.7,  the DMA IP(v7.1)  is All applicable in VIVADO and ISE?


I use the DMA SG mode ,Program the DMA IP driver in linux, I allocate buffer for DMA, and connect the buffer in Circular buffer.

The Built-in DMA driver in linux xilinx_axidma.c ,I modify it to enable cyclic BD mode like blow  my attachment.


2)、My second question ,The Built-in DMA driver xilinx_axidma.c in linux-xlnx-xilinx-v2013.4,have  xilinx_axidma.c modified to support cyclic BD mode?


if  the above two question is YES. I test the  DMA transfer ,However,when data transfered to the last buffer descriptor ,The s_axis_s2mm_sts_tready  signal  at AXI DMA interface pulled down ,then the DMA suspend transmission.


3)、Third question , Why the s_axis_s2mm_sts_tready  signal  at AXI DMA interface pulled down? Should it  run forever in cyclic mode ?


 Any insight will be appreciated! 





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Observer qswsjs
Registered: ‎07-18-2013

Re: AXI DMA7.1 Cyclic mode problem

 I think the DMA IP(v7.1) is applicable ISE14.7, because I can transfer data to the last BD.Now I dont know whether I have enabled the cyclic BD mode successfully? Or if I have enabled cyclic BD mode (cyclic BD mode enable bit in S2MM DMA control register to 1),why it doesnt work in cyclic BD mode?

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