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Observer rdennen91
Registered: ‎03-08-2016

AXI Quad SPI Timeouts on Zynq7000 Petalinux 2018.2


I'm integrating an external flash memory (non-boot) in a ZC706-based design. I've added an AXI Quad SPI IP core in Quad mode to drive it. The Zynq PS must be able to read this device from an FMC card.

For now I'm using the SPIDEV driver to verify the connection. Each time I try to run data, I get the follow "timeout" error.

root@xilinx-zc706-2018_2:~# echo hello > /dev/spidev1.0
spidev spi1.0: SPI transfer timed out
-sh: echo: write error: Connection timed out

I've seen some previous posts about bugs in the SPI driver related to 2017.x that I was originally using. I tried disabling the CONFIG_PM kernel option with no success. That's when I updated to 2018.2 (the newest I have available). Maybe I still need an external Xilinx kernel?

Using devmem, I can verify that the core is readable/writable. I see that the TX FIFO occupancy increases with each echo command, but never seems to empty.

I should also note I tried setting the core to mode 0 (standard SPI) and got the same error.

With the project deadline rapidly approach, I'm pretty desparate to get this to work. Alternative approaches are also welcome. I just need to be able to read from an external QSPI flash over PL pins (on an FMC card, not using the PS boot QSPI)

EDIT: I forgot to mention I have an ILA on the SPI output pins. I only see the chip select correctly set to zero. The SCK output, however, never seems to toggle. I am not using the STARTUP primitive option, which seems to disable this functionality.

Tool chain:

Vivado/Petalinux 2018.2

Device tree (system-user.dtsi)

axi_quad_spi_0: axi_quad_spi@44000000 {
compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
reg = <0x44000000 0x10000>;
xlnx,fifo-depth = <0x200>;
#address-cells = <0x1>;
#size-cells = <0x1>;
status = "okay";

spidev@0x0 {
reg = <0>;
status = "okay";

Thank you


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