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5,036 Views
Registered: ‎04-11-2017

AXI read hangs

Hi, We are trying to run the latest versions on master branch of linux-xlnx (4.9 kernel) and u-boot-xnlx on a zynqmp(xczu3eg) board with our own Yocto recipes. We previously ran something based on 4.6 and the upgrade to latest on 4.9 and Vivado 2017.1. This upgrade has solved some of our previously problems but now we have a new one:


We have 8 AXI timers in the FPGA accessed with our own driver and when we try to read from them everything hangs.

Our pl.dtsi (included in our device tree) looks like this:

 

/ {
	amba_pl: amba_pl@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges ;
		axi_timer_0: timer@a0000000 {
			clock-frequency = <99998999>;
			clocks = <&misc_clk_0>;
			compatible = "xlnx,xps-timer-1.00.a";
			interrupt-parent = <&gic>;
			interrupts = <0 89 4>;
			reg = <0x0 0xa0000000 0x0 0x10000>;
			xlnx,count-width = <0x20>;
			xlnx,gen0-assert = <0x1>;
			xlnx,gen1-assert = <0x1>;
			xlnx,one-timer-only = <0x0>;
			xlnx,trig0-assert = <0x1>;
			xlnx,trig1-assert = <0x1>;
		};
		axi_timer_1: timer@a0010000 {
		..
		};
		..
		..
		axi_timer_7: timer@a0070000 {
		..
		};psu_ctrl_ipi: PERIPHERAL@ff380000 {
			compatible = "xlnx,PERIPHERAL-1.0";
			reg = <0x0 0xff380000 0x0 0x80000>;
		};
		psu_message_buffers: PERIPHERAL@ff990000 {
			compatible = "xlnx,PERIPHERAL-1.0";
			reg = <0x0 0xff990000 0x0 0x10000>;
		};
		misc_clk_0: misc_clk_0 {
			#clock-cells = <0>;
			clock-frequency = <99998999>;
			compatible = "fixed-clock";
		};
	};
};

This also hangs:
>devmem2 0xa0000000

 


So any idea how to solve this? It worked with a previous kernel.

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10 Replies
4,990 Views
Registered: ‎04-11-2017

In our dts file I changed the include from:

/include/ "zynqmp-clk-ccf.dtsi"

to: 

/include/ "zynqmp-clk.dtsi"

and then it seemed to work, but this doesn't seem to be the correct solution. As I understand it some other components that we are going to use is dependent on the common clock framework.

So perhaps we can use the common clock framework if we change misc_clk_0 to something else?

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Adventurer
Adventurer
4,431 Views
Registered: ‎05-07-2008

Thank you for posting your solution. I was experience the same issue when trying to access my AXI_IIC controllers. Your solution fixed my problem. too

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Xilinx Employee
Xilinx Employee
4,414 Views
Registered: ‎10-06-2016

Hi per.h.johnsson@afconsult.com

 

From where is coming that miscellaneous clock? Is it an external clock?

Are you loading the PMU FW?


Ibai
Don’t forget to reply, kudo, and accept as solution.
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Adventurer
Adventurer
4,400 Views
Registered: ‎05-07-2008

For me at least, the device tree files are generated by SDK.

Yes, the PMU FW is loaded.

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Xilinx Employee
Xilinx Employee
4,268 Views
Registered: ‎08-01-2007

I guess Linux turned off PL clock. Try to add "clk_ignore_unused" in bootargs and check the results.

 

Adventurer
Adventurer
4,087 Views
Registered: ‎05-07-2008

I went back to using zynqmp-clk-ccf.dtsi and added "clk_ignore_unused: to my bootargs.

AXI accesses to IP in the PL works again. Thanks

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Xilinx Employee
Xilinx Employee
4,035 Views
Registered: ‎10-06-2016

Hi @jawbone_101. Could you mark the issue as solved? This help us to track which are the open thread :)

Ibai
Don’t forget to reply, kudo, and accept as solution.
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Adventurer
Adventurer
4,030 Views
Registered: ‎05-07-2008

Hi,

I did not start this thread so I do not think I should mark it solved.

I just contributed and posted my results in case it helps anyone else.

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Xilinx Employee
Xilinx Employee
4,027 Views
Registered: ‎10-06-2016

Hi @jawbone_101, you are right the user that started the post needs to mark it as solved :)

I thought you created the post, my fault.

Ibai
Don’t forget to reply, kudo, and accept as solution.
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Observer
Observer
2,105 Views
Registered: ‎04-30-2013

Hi, we also ran into this same issue, and we are now able to read axi space after using the bootarg shown.

 

Based on  Documentation/clk.txt, it seems like this is not a good long term solution though, what do you think?

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