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Explorer
Explorer
5,082 Views
Registered: ‎02-18-2014

Axi Uartlite - Baudrate Support

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I've found documentation and forums that seem to have conflicting information. Based on PG142-axi-uartlite.pdf it appears that the baudrate of a axi uartlite block is only configurable by hardcoding it in logic, while other forums posts appear to imply that uartlite's support termios?

 

Which is the case?

 

I've written up the code that sets termios settings for the axi-uarts as well as my 2 console uarts, however the code only affects the console uarts and appears to be ignored by the axi-uartlites. Am found some example code at the following location "C:\Xilinx_2014.4\SDK\2014.4\data\embeddedsw\XilinxProcessorIPLib\drivers\uartlite_v3_0\src\xuartlite.c" that claims "The baudrate and format of the data are fixed in the hardware at hardware build time."

 

So do axi-uartlites not support dynamic baud rate changes?

 

Thanks!

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Xilinx Employee
Xilinx Employee
8,529 Views
Registered: ‎01-21-2014

Re: Axi Uartlite - Baudrate Support

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The baud rate is fixed in hardware for AXI UARTLite.  There is a "full" AXI UART soft IP core available with dynamic baudrate. 

 

Terry

 

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2 Replies
Xilinx Employee
Xilinx Employee
8,530 Views
Registered: ‎01-21-2014

Re: Axi Uartlite - Baudrate Support

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The baud rate is fixed in hardware for AXI UARTLite.  There is a "full" AXI UART soft IP core available with dynamic baudrate. 

 

Terry

 

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Explorer
Explorer
5,074 Views
Registered: ‎02-18-2014

Re: Axi Uartlite - Baudrate Support

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Thats what i thought, thanks for the quick reply Terry. We are limited on space in the PL so i was hoping to find another way, but its great to know with confidence the correct answer!

 

Thanks again

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