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Explorer
Explorer
5,512 Views
Registered: ‎07-14-2008

BlueCat, BSP and External Interrupts

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Hello everyone,

 

sorry if this is an old topic, but using the search feature on this site yielded no results for the problem. The problem we're facing is as follows:

 

  • We're building a signalprocessor with embedded microblaze on which a BlueCat linux distro runs
  • Outside of the microblaze but inside the FPGA are a few modules that generate interrupts
  • These signals are connected to the microblaze's interrupt controller xintc
  • In the MHS file, these signals are clearly marked as interrupts via the SIGIS attribute

 

When i run the BSP generation for standalone, these #defines are generated in the xparameters.h

 

#define XPAR_PROCESSOR_CORE_V1_0_FPGA_0_IRQ_PIF_MASK 0X000001
#define XPAR_XPS_INTC_0_PROCESSOR_CORE_V1_0_FPGA_0_IRQ_PIF_INTR 0
#define XPAR_PROCESSOR_CORE_V1_0_FPGA_0_IRQ_IR_MASK 0X000002
#define XPAR_XPS_INTC_0_PROCESSOR_CORE_V1_0_FPGA_0_IRQ_IR_INTR 1
#define XPAR_XPS_TIMER_1_INTERRUPT_MASK 0X000004
#define XPAR_XPS_INTC_0_XPS_TIMER_1_INTERRUPT_INTR 2
#define XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK 0X000008
#define XPAR_XPS_INTC_0_ETHERNET_MAC_IP2INTC_IRPT_INTR 3
#define XPAR_RS232_UART_1_INTERRUPT_MASK 0X000010
#define XPAR_XPS_INTC_0_RS232_UART_1_INTERRUPT_INTR 4

 

which is exactly what we wanted.

 

However, when my colleague runs the BSP generation for BlueCat, the result is

 

#define XPAR_PROCESSOR_CORE_V1_0_0_IRQ 0
#define XPAR_TIMER_0_IRQ 2
#define XPAR_ETHERNETLITE_0_IRQ 3
#define XPAR_UARTLITE_0_IRQ 4

accompanied by the following warning from the generator

 

#--------------------------------------
# Linux BSP generate...
#--------------------------------------
Copying Library Files ...
Running post_generate for OS'es, Drivers and Libraries ...
Warning: ignoring redefinition of PROCESSOR_CORE_V1_0_0_IRQ

 

My theory is, the generator tries to create the symbol name, but truncates the name due to some obscure rule. The next name for the second IRQ results in the same truncated symbol name and thus, results into this warning.

 

The signals are declared in the MHS as follows:

 

PORT FPGA_0_IRQ_PIF = fpga_0_IRQ_PIF, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
PORT FPGA_0_IRQ_IR = fpga_0_IRQ_IR, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING

 

and are connected to the XINTC as follows:

 

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Irq = Interrupt
 PORT Intr = RS232_Uart_1_Interrupt&Ethernet_MAC_IP2INTC_Irpt&xps_timer_1_Interrupt&fpga_0_IRQ_IR&fpga_0_IRQ_PIF
END

 

Now, if you have any idea about the cause of this error, i'd appreciate any help.

 

 

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1 Solution

Accepted Solutions
Explorer
Explorer
6,172 Views
Registered: ‎07-14-2008

Work-Around found (Re: BlueCat, BSP and External Interrupts)

Jump to solution

After some testing i found out that there seems to be some restriction in effect for the BlueCat BSP generation. It appears that neither peripheral components nor the toplevel entity is allowed to have more than one interrupt signal port. Maybe it's just a bug.

 

For the work-around i created a small synchronization IP core that takes external signal (former interrupt) and outputs an interrupt signal. The interrupt signal is being marked as such by the IP's MPD file:

 

PORT Synced_Signal = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING

 

Now, for every external signal that is to be treated as an interrupt source, once instance of this IP core has to be added. The MHS then looks like this:

 

PORT FPGA_0_IRQ_PIF = fpga_0_IRQ_PIF, DIR = I
PORT FPGA_0_IRQ_IR = fpga_0_IRQ_IR, DIR = I

 

BEGIN IRQ_Signal_Synchronizer
 PARAMETER INSTANCE = PIF_IRQ_Signal_Synchronizer
 PORT Clock = sys_clk_s
 PORT Reset = sys_rst_s
 PORT Unsynced_Signal = fpga_0_IRQ_PIF
 PORT Synced_Signal = PIF_IRQ_Synced
END

BEGIN IRQ_Signal_Synchronizer
 PARAMETER INSTANCE = IR_IRQ_Signal_Synchronizer
 PORT Clock = sys_clk_s
 PORT Reset = sys_rst_s
 PORT Unsynced_Signal = fpga_0_IRQ_IR
 PORT Synced_Signal = IR_IRQ_Synced
END

 

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Irq = Interrupt
 PORT Intr = RS232_Uart_1_Interrupt&Ethernet_MAC_IP2INTC_Irpt&xps_timer_1_Interrupt&PIF_IRQ_Synced&IR_IRQ_Synced
END

 

Though this work-around works and ain't bad in style, i still would appreciate if someone could get this bug fixed.

 

0 Kudos
1 Reply
Explorer
Explorer
6,173 Views
Registered: ‎07-14-2008

Work-Around found (Re: BlueCat, BSP and External Interrupts)

Jump to solution

After some testing i found out that there seems to be some restriction in effect for the BlueCat BSP generation. It appears that neither peripheral components nor the toplevel entity is allowed to have more than one interrupt signal port. Maybe it's just a bug.

 

For the work-around i created a small synchronization IP core that takes external signal (former interrupt) and outputs an interrupt signal. The interrupt signal is being marked as such by the IP's MPD file:

 

PORT Synced_Signal = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING

 

Now, for every external signal that is to be treated as an interrupt source, once instance of this IP core has to be added. The MHS then looks like this:

 

PORT FPGA_0_IRQ_PIF = fpga_0_IRQ_PIF, DIR = I
PORT FPGA_0_IRQ_IR = fpga_0_IRQ_IR, DIR = I

 

BEGIN IRQ_Signal_Synchronizer
 PARAMETER INSTANCE = PIF_IRQ_Signal_Synchronizer
 PORT Clock = sys_clk_s
 PORT Reset = sys_rst_s
 PORT Unsynced_Signal = fpga_0_IRQ_PIF
 PORT Synced_Signal = PIF_IRQ_Synced
END

BEGIN IRQ_Signal_Synchronizer
 PARAMETER INSTANCE = IR_IRQ_Signal_Synchronizer
 PORT Clock = sys_clk_s
 PORT Reset = sys_rst_s
 PORT Unsynced_Signal = fpga_0_IRQ_IR
 PORT Synced_Signal = IR_IRQ_Synced
END

 

BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Irq = Interrupt
 PORT Intr = RS232_Uart_1_Interrupt&Ethernet_MAC_IP2INTC_Irpt&xps_timer_1_Interrupt&PIF_IRQ_Synced&IR_IRQ_Synced
END

 

Though this work-around works and ain't bad in style, i still would appreciate if someone could get this bug fixed.

 

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