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Visitor vsergeevk
Visitor
6,220 Views
Registered: ‎01-06-2014

BootGen adding extra bytes and u-boot Zynq PL FPGA load nuances

Hello,

 

It seems that the latest BootGen (Build-14.7, Date-Sept 12, 2013) is adding 4 extra bytes when used to convert a bitstream into binary format.

 

 

$ bootgen

Xilinx BootGen
Build-14.7, Date-Sept 12, 2013
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

bootgen
     [-image FILENAME[.bif]]
     [-split <mcs | bin>]]
     [-fill [<hex_byte>]]
     [-o FILENAME(.mcs|.bin)]
     [-p PARTNAME]
     [-w [on|off]]
     [-h ]
     [-encrypt [bbram | efuse] [StartCBC=<hex_string>] [Key0=<hex_string>] [HMAC=<hex_string>] [FILENAME[.nky]]]
     [-efuseppkbits FILENAME]
     [-generate_hashes]
     [-legacy]
     [-padimageheader[=(0|1)]
     [-debug ]

$ ls
boot.bif  fsbl.elf  system.bit  u-boot.elf
$ du -b system.bit
4045662	system.bit
$ cat boot.bif
image : {
	[bootloader]fsbl.elf
	u-boot.elf
	system.bit
}
$ bootgen -image boot.bif -split bin -o -i BOOT.bin
$ ls
boot.bif  boot.bin  fsbl.elf  system.bit  system.bit.bin  u-boot.elf  u-boot.elf.bin
$ du -b system.bit.bin
4045568	system.bit.bin
$

 

system.bit.bin should be exactly 4045564 bytes for the Z7020 device.

 

I can check the bitstream's actual size in the "e" key of the bitstream header:

$ dd if=system.bit bs=1 count=100 | hexdump -C
100+0 records in
100+0 records out
100 bytes (100 B) copied, 0.000131854 s, 758 kB/s
00000000  00 09 0f f0 0f f0 0f f0  0f f0 00 00 01 61 00 24  |.............a.$|
00000010  5a 37 30 32 30 50 4c 49  4f 5f 77 72 61 70 70 65  |Z7020PLIO_wrappe|
00000020  72 3b 55 73 65 72 49 44  3d 30 58 46 46 46 46 46  |r;UserID=0XFFFFF|
00000030  46 46 46 00 62 00 0c 37  7a 30 32 30 63 6c 67 34  |FFF.b..7z020clg4|
00000040  30 30 00 63 00 0b 32 30  31 34 2f 30 31 2f 30 36  |00.c..2014/01/06|
00000050  00 64 00 09 31 35 3a 30  32 3a 33 39 00 65 00 3d  |.d..15:02:39.e.=|
00000060  ba fc ff ff                                       |....|
00000064
$

which is 0x003dbafc = 4045564. Apparently after stripping this 98 byte header, the file size should be 4045662 (system.bit total size) - 98 (header size) = 4045564, but it is 4045568, so BootGen is adding an additional 4 extra bytes to the end.

 

This is a problem for u-boot, because it ( https://github.com/Xilinx/u-boot-xlnx/blob/c55c35bb239a40d5d5d7678fc38b92c77cf882f8/drivers/fpga/zynqpl.c#L165 ) believes it is working with a parial bitstream when it is provided a size not equal to the FPGA's size, and it doesn't complete the FPGA configuration.

 

For anyone encountering this problem, I've been using two workarounds:

 

#1 Explicitly specify the right bitstream size (0x3dbafc for ZC7020) during the fpga load in u-boot. This effectively crops the 4 extra bytes that BootGen decides to tack on for fun.

... <download bitstream to ${loadbit_addr}> ...
zynq-uboot> fpga info 0
...
zynq-uboot> fpga load 0 ${loadbit_addr} 0x3dbafc
...

Note that "fpga load" in u-boot requires the size to be specified in hexadecimal. It will interpret decimal values as hexadecimal.

 

#2 Use a tool like milosoftware's fpga-bit-to-bin.py python script: http://forums.xilinx.com/t5/Embedded-Linux/Zynq-Loading-bitfile-into-FPGA-from-Linux-xdevcfg/m-p/353497#M6805 , now available here https://github.com/milosoftware/meta-zynq/tree/master/recipes-bsp/fpga/fpga-bit-to-bin . This will produce the correctly sized binary bitstream file, and let you hold on to the ${filesize} environment variable in u-boot when you download the bitstream from TFTP, MMC, etc. instead of hardcoding the device size. This keeps the u-boot environment general for different sized zynq devices.

 

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3 Replies
Visitor vsergeevk
Visitor
6,197 Views
Registered: ‎01-06-2014

Re: BootGen adding extra bytes and u-boot Zynq PL FPGA load nuances

Sorry, this BootGen is from the 2013.3 SDK release. I am going to try the 2013.4 release and check if the issue is fixed.

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Visitor vsergeevk
Visitor
6,192 Views
Registered: ‎01-06-2014

Re: BootGen adding extra bytes and u-boot Zynq PL FPGA load nuances

This seems to still be an issue with BootGen in 2013.4.

 

Xilinx BootGen
Build-2013.4, Date-Oct 31, 2013
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

bootgen
     [-image FILENAME[.bif]]
     [-split <mcs | bin>]]
     [-fill [<hex_byte>]]
     [-o FILENAME(.mcs|.bin)]
     [-p PARTNAME]
     [-w [on|off]]
     [-h ]
     [-encrypt [bbram | efuse] [StartCBC=<hex_string>] [Key0=<hex_string>] [HMAC=<hex_string>] [FILENAME[.nky]]]
     [-efuseppkbits FILENAME]
     [-generate_hashes]
     [-legacy]
     [-padimageheader[=(0|1)]
     [-debug ]

 

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Xilinx Employee
Xilinx Employee
6,145 Views
Registered: ‎01-15-2014

Re: BootGen adding extra bytes and u-boot Zynq PL FPGA load nuances

The extra bytes are padded to the partition (say bitstream) to the 32-byte aligned boundary. This is PCAP DMA requirement.
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