12-28-2017 06:59 AM
I've designed a pcb with a XC7Z020-1CLG400C and I'm trying to boot Linux from the SD card.
What I've done so far:
1) formatted the SD card for SD boot as shown here: www.wiki.xilinx.com/How+to+format+SD+card+for+SD+boot
2) downloaded the ug1165-zynq-embedded-design-tutorial.zip file from UG1165 page 124
3) on SDK, I've created a BOOT.bin file following UG1165 page 90. I've used both fsbl.elf and u-boot.elf from the zip file downloaded and I've included my FPGA .bit file
4) Copied BOOT.bin and image.ub (downloaded from the zip file) into the SD card
5) Set my board to boot from SD card, insert SD card, switch the power on
Now, I believe that there's nothing being loaded as my FPGA is not being programmed and my pcb is not drawing any more current.
I can program the FPGA using SD card (also by QSPI and JTAG) without any problems, so this end should be OK.
On my step no. 3, I have also tried with a fsbl.elf I created from scratch using SDK.
Could someone spot any mistake I'm making? Or any missing steps?
Thanks in advance!
01-19-2018 03:05 AM
01-02-2018 08:04 PM
Step 1 is to run some bare-metal tests first. Hopefully you pulled DONE on your PCB to an LED via a pull up resistor. (likewise Vivado's programmer should be able to detect whether the DONE was successful). Did you follow UG933 for the PCB layout?
Use some LEDs or test points as pinout to see if you can successfully program a simple bitstream to verify the FPGA side of things.
Step 2: Then, if you can ensure that you can program a bare-bitstream, export to SDK from Vivado, but just do hello-world to make sure that you can see the UART output as expected. Do you? Then move on below to step 3. Otherwise you have some issues. First, check the linker script to make sure that the hello world is linked to OCM and not DDR. Does it work in OCM but not DDR? you probably have calibration issues. Did you input the trace lengths/propagation delays into the IP-Integrator Zynq block? Did you follow the UG933 layout guidelines for DDR?
If you can't get OCM based hello-world, pull out the voltmeter and test Vccint, Vccaux, Vccpint, etc. are they all expected values and sequence from the datasheet DS187?
Is your ARM clock (PS_CLK) a rock solid 33.3333MHz?
Step 3: The FSBL that is included in that application note is specifically built for the ZC702, which is a XC7Z020-1CLG484. The FSBL sets up all the MIO/peripheral controllers specifically to match that specific board's Vivado export. In SDK, build your own FSBL, it's an easy one step process, as there is rarely user-intervention required (File -> New Application Project -> Zynq FSBL). Looks like you've tried this. You can also add "#define FSBL_DEBUG_INFO" to main.c to get some early print statements from the FSBL.
Depending on whether you used the exact same peripherals (like UART console), memory sizes, etc. there is a moderate chance that you'll need to make some modifications to that stock u-boot.elf file too.
Let's start with this and see what you have.
01-19-2018 03:05 AM