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Observer
Observer
1,049 Views
Registered: ‎07-08-2019

Booting PetaLinux from Dual Quad-SPI, MicroBlaze and KCU105

I'm trying to run PetaLinux on MicroBlaze using the KCU105 board. I'm using the PetaLinux 2018.3 workflow.

So far, I've successfully booted PetaLinux by downloading both the bitstream and kernel via JTAG. However, I would like to be able to boot from the Dual QSPI so I don't have to boot via JTAG each time. 

In Vivado, I included the following constraints for the flash memory:

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
set_property CONFIG_MODE SPIx8 [current_design]

In PetaLinux, after building the image, I use the following command to create the primary and secondary .mcs files:

petalinux-package --boot --force --fpga <path to .bit> --u-boot --kernel --flash-size 64 --flash-intf SPIx8

I then use the Hardware Manager in Vivado to Add Configuration Memory Device (mt25qu256-spi-x1_x2_x4_x8) then program the device withe the two .mcs files generated from the above command. 

When I reboot the board, the "Done" LED lights up, but the image does not boot. It seems as though the bitstream is gets loaded, but then doesn't know how to jump to the u-boot.

Any help would be appreciated. I attempted to upload the primary .mcs file, but it exceeds the upload size limit.

Thanks,

Steve

8 Replies
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Xilinx Employee
Xilinx Employee
939 Views
Registered: ‎10-12-2018

Hi @smbrown ,

Are you using AX QSPI IP to access the flash memory?

Please refer xapp1280 which demonstrates the post configuration access between kintex ultrascale FPGA and SPI flash memory provided by a kcu105 evaluation board.

https://www.xilinx.com/support/documentation/application_notes/xapp1280-us-post-cnfg-flash-startupe3.pdf

This XAPP1280 also provides reference designs for quick start.

Thanks & Regards
Anil B
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Observer
Observer
895 Views
Registered: ‎07-08-2019

I have followed XAPP1280 to include the AXI QSPI IP in my block design and the STARTUP3 block in my top level wrapper. I change modes from SPIx8 to SPIx4 and included the appropriate constraints in my .xdc file based on those given in the app note. I followed the example given XAPP1280 to create and load my own "Hello World" application from flash using the SREC SPI Bootloader in SDK. That all works fine and the program boots from flash each time the board is turned on (or when I press the PROG button).

As I move over to PetaLinux, like I previously mentioned, I'm able to download both the bitstream and kernel image to the board using the petalinux-boot --jtag command, and login, but I'm still not able to boot from the QSPI flash.

Referencing UG1157 (2018.3), starting on page 22, I used the following command to create the MCS file for the MicroBlaze (I ran the command from the images/linux/ directory in my PetaLinux project):

 

petalinux-package --boot --force --format MCS --fpga ../../project-spec/hw-description/kcu105_wrapper.bit --mmi ../../project-spec/hw-description/kcu105_wrapper.mmi --fsbl fs-boot.elf --u-boot u-boot-s.bin --kernel image.ub --flash-size 32 --flash-intf SPIx4 --output kcu105_test.mcs

The terminal output confirms that the bitstream, u-boot, and the kernel image are all added to the correct offsets in flash according to the partitions I setup in the menuconfig primary flash partition table settings. The MCS file (kcu105_test.mcs) is successfully generated.

petalinux-package.png

 

 

 

 

 

 

I then use Vivado to Add Configuration Memory Device (mt25qu256-spi-x1_x2_x4) and program it with the kcu105_test.mcs file and give the following Programing Operations:

  • Address Range: Entire Configuration Memory Device
  • Erase: Y
  • Blank Check: N
  • Program: Y
  • Verify: Y
  • Verify Checksum: N

The device programs, and when I power cycle the board, all I see is information about the FS-Boot, and it stalls indefinitely:


fs-boot.png

 

 

 

 

 

 

 

 

 

 

 

 

 

 

From UG1144 (2018.3), page 132, FS-Boot needs the CONFIG_FS_BOOT_START macro defined to know where in flash to get the image, but the PetaLinux tool sets this macro automatically from the flash partition settings, and that the start is the begining of the boot partition (where my u-boot is located). That being the case, I'm not sure what I'm missing, but it doesn't seem like the FS-Boot is finding and loading the u-boot. Is there something in the configuration settings I'm missing?

Thanks for any help!

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Xilinx Employee
Xilinx Employee
810 Views
Registered: ‎10-12-2018

Hi @smbrown ,

Apologies for delay in response, Looks the steps/commands that you have followed are fine to me.

To narrow down this issue, Can you please use prebuilt petalinux bsp for kcu105 board and use the same command/steps (you have mentioned in previous post ) for generating the MCS file after petalinux build? If this will work fine, we will get a clue that something you are missing in your hardware design. So that we can compare with reference block design to resolve this issue.

Thanks & Regards
Anil B
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Observer
Observer
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Registered: ‎07-08-2019

Hi @abommera,

I built PetaLinux from the KCU105 BSP PetaLinux project using the same workflow as previously outlined, and everything worked just fine booting from flash. 

I opened up the hardware design under <plnx_proj>/hardware/xilinx-kcu105-axi-full-2018.3/ and compared it with my own. The key difference I found was the AXI Quad SPI IP in the BSP hardware project uses the STARTUP Primitive Internal to the IP. I changed my own design to also use the STARTUP Primitive Internal to the QSPI IP, and I was able to get everything to boot properly. 

I'm not sure why my prior setup of using the STARTUP Primitive External to the IP didn't work for booting PetaLinux, when it worked just fine following the XAPP1280 for using a SREC SPI Bootloader. If you have any insight to this, that would be helpful.

Thanks!

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Xilinx Employee
Xilinx Employee
739 Views
Registered: ‎10-12-2018

Hi @smbrown ,

Glad to know that the issue has been resolved with startup primitive internal to the IP. The functionality would be the same for primitive internal and external to the IP. The only difference is the way of accessing the STARTUPE3 signals.

If a design requires multiple cores should use STARTUPE3, then use STARTUPE3 primitive external to the IP to visible external to the AXI QSPI IP core.

If a user design only requires STARTUPE3 port access with the AXI Quad SPI core then use startup primitive to internal to the IP.

Thanks & Regards
Anil B
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Observer
Observer
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Registered: ‎05-16-2018

Hi @smbrown and @abommera,
Thank you for the detailed comments - they are very helpful. Perhaps you can help me with a follow up question? I am trying to run a similar design on an Alveo board. I configured the STARTUPE3 Primitive as "Internal to the IP" but am not sure how to connect the SPI related signals from the wrapper. Was there any change in the wrapper connections on your end when you went from External to Internal? My attempt to simply map the design pins to a STARUPE3 instance gave an implementation error stating that multiple STARTUPE3 instances are declared.
Thank you very much!
I'll keep editing this reply as I figure things out.
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Observer
Observer
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Registered: ‎07-08-2019

Hi@sm7ed,

If you choose to have the STARTUPE3 primitive instantiated "Internal to the IP," then you do not need to include the primitive instantiation in your top level wrapper. Try removing the instantiation in your wrapper, and let the SPI IP handle the primitive.

Steve

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Observer
Observer
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Registered: ‎05-16-2018

Hi @smbrown @abommera and dear world, please help!

This being a different board (Alveo U280 ES1) and with no reference design using the STARTUPE3 available for it, despite the very helpful comments here, best I could do so far is to get stuck with the same message:

FS-BOOT First Stage Bootloader (c) 2013-2014 Xilinx Inc.
Build date: Jun 22 2020 21:13:44 
Serial console: Uart16550

In detail, here is what I do. I create a project targeting the Alveo U280 ES1 board in Vivado 2019.2 with a block design consisting of the DDR4-C1, MicroBlaze, AXI Timer, UART and AXI Quad SPI. The block design, connections and addresses are depicted below. The MicroBlaze is configured as "Low-end Linux with MMU" so it's 32-bit with interrupt, basic debug, caches and the only change is that I enabled the "Peripheral AXI Instruction Interface". The AXI timer has both timers enabled. The AXI Quad SPI is configured with {Enable Performance Mode, Quad mode, 1 Micron Slave device, FIFO Depth 256, Flash access through STARTUP Primitive enabled and set to use Internal to IP}.

Block Design with MicroBlaze, DDR4 and AXI Quad SPIBlock Design with MicroBlaze, DDR4 and AXI Quad SPI

 MicroBlaze Address SpaceMicroBlaze Address Space

The Block design passes verification, then I generate the wrapper. Additionally, I include a constraints file as instructed in the Alveo U280 User Guide. Constraints file content:

# Bitstream Configuration
# ------------------------------------------------------------------------
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]
# ------------------------------------------------------------------------

The design meets timing (100MHz everywhere other than 300MHz DDR4 interface) and all pins (clk, rst, ddr4) automatically connect correctly thanks to the board files (verified after synthesis in IO window). With the implementation open I export the design including the bitstream.

Next, to create the PetaLinux project, I run:

petalinux-create --type project --template microblaze --name PetaLinuxStE3i
mv MicBlzDDR4StE3Lnx_wrapper.xsa PetaLinuxStE3i/ && cd PetaLinuxStE3i/
petalinux-config --get-hw-description=. --silentconfig
petalinux-config
# here I increase the size of the Flash partitions to fit the bitstream and kernel (image below) petalinux-config -c rootfs petalinux-build
# and it builds with no issues, then, to get the MCS petalinux-package --boot --force --format MCS --fpga project-spec/hw-description/MicBlzDDR4StE3Lnx_wrapper.bit --offset 0x01002000 --mmi project-spec/hw-description/MicBlzDDR4StE3Lnx_wrapper.mmi --fsbl images/linux/fs-boot.elf --u-boot images/linux/u-boot-s.bin --kernel images/linux/image.ub --flash-size 1024 --flash-intf SPIx4 --output MicBlzDDR4Lnx.mcs

PetaLinux Configuration for Flash PartitionsPetaLinux Configuration for Flash Partitions

The first 16MB of the SPI Flash on the Alveo U280 board are locked, therefore I allocate more space (44MB) for partition 0 and offset the bitstream to 0x01002000.

Next, I open the device in Hardware Manager, program the memory device (mt25qu01g-spi-x1_x2_x4) and then "Boot from Configuration Memory Device" the FPGA device (to avoid a cold, am remote...). Sadly, the only message coming from the FPGA board are the 3 lines listed in the beginning.

Failing Boot from MCS on SPI FlashFailing Boot from MCS on SPI Flash

Clearly, the issue has to be with the MCS file or with the Quad SPI Flash configuration, because I am able to successfully boot via JTAG with:

petalinux-boot --jtag --kernel --fpga --xsdb-conn "connect; targets 6" -v

Successful boot via JTAGSuccessful boot via JTAG

Any suggestions would be super helpful. How can I debug better the bootloader? What documentation would be helpful to read? Thank you very much!

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