08-13-2017 10:29 PM
This is my first post here providing some info and looking for some help...
I followed the xilinx example design "AR# 50826 Zynq-7000 Example Design - Cache coherent CDMA transfers from block RAM to OCM".
For convenience, here is the system diagram:
The baremetal case works fine (you download the xilinx example at here). However we are trying to make it work under user space.
Attached is a working code example without using DMA device driver.
It is adopted from the xilinx example code, I used mmap to access physical address.
To get it working I have to flush the cache several times before reading.
I have following questions:
1) The address map is as follows:
|Data (32 address bits : 0x40000000 [ 1G ])|
|Data (32 address bits : 4G)|
|Unmapped Slaves (2)|
As you can see that the axi_bram_ctrl_1 is at address 0x8000_0000, and in the code we have:
char * srcDMA = (char *) 0x80000000; // from BRAM char * srcCPU = (char *) 0x70000000; // from BRAM char * dstDMA = (char *) 0x001F8000; // to DDR char * dstCPU = (char *) 0x001F8000; // to DDR
The srcDMA points to bram controller (0x80000000).
Here comes my question: Where is the address map for CDMA? That is, we have the address map for processors in system.hdf, do we have address map for CDMA (i.e. which address can the CDMA access ddr, is it the same as that in processor map table)?
2) Why do I need to flush the cache? Should not the ACP make the cache coherent so I do not need to flush manually?
if I do not flush cache, the read back is corrupted with 0xCD sometimes (please try out my attached code).
3) what is the right way to do the DMA in user space using AXI-CDMA ?
(my way of bypassing the linux DMA driver does not seem to be orthodox...)
Any advice are greatly appreciated.