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Participant ejubenville
Participant
836 Views
Registered: ‎10-17-2008

Cadence I2C timeouts on PicoZed, no pin activity

I can't get the hard I2C 0 core to work in a PicoZed. A probe using "i2cdetect -r 0" results in the following timeout error for all I2C addresses:

cdns-i2c e0004000.i2c: timeout waiting on completion

I see no activity on the SDA/SCL pins coming out of the chip, so I think I must have a configuration problem. In Vivado, I’ve mapped I2C0 to MIO pins 50 (SCL) and 51 (SDA), and exported the ps7_init_gpl.* files needed for uboot in my buildroot configuration. Following is the relevant portion of ps7_init_gpl.c to initialize MIO 50 and 51 pin configurations:

// .. TRI_ENABLE = 0
// .. L0_SEL = 0
// .. L1_SEL = 0
// .. L2_SEL = 0
// .. L3_SEL = 2
// .. Speed = 1
// .. IO_Type = 1
// .. PULLUP = 1
// .. DisableRcvr = 0
EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001340U),
// .. TRI_ENABLE = 0
// .. L0_SEL = 0
// .. L1_SEL = 0
// .. L2_SEL = 0
// .. L3_SEL = 2
// .. Speed = 1
// .. IO_Type = 1
// .. PULLUP = 1
// .. DisableRcvr = 0
EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001340U),

My device tree setup for i2c0 is (including an EEPROM device on the bus):

i2c@e0004000 {
  compatible = "cdns,i2c-r1p10";
  clocks = <&clkc 0x26>;
  interrupts = <0 25 4>;
  i2c-clk = <400000>;
  reg = <0xE0004000 0x1000>;
  #address-cells = <0x1>;
  #size-cells = <0x0>;          
  eeprom: eeprom@90 {
    compatible = "at,24c08";
    reg = <0x90>;
    };  
};

The versions of the tools involved with the build:

Vivado 2017.4
buildroot-2017.11.2
linux-xilinx-v2017.2 (includes i2c-cadence.c driver)
uboot-xilinx-v2017.2

Am I missing a configuration step somewhere?  Why can't I see any activity on the MIO 50 and 51 pins during i2cdetect?

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3 Replies
Contributor
Contributor
829 Views
Registered: ‎04-04-2018

Re: Cadence I2C timeouts on PicoZed, no pin activity

Where you're monitoring the signals?

 

ATM I don't have a picoZed board to inspect ... but I'm curious about the state of "S1" switch that I see on the schematic (pg 3, C-4) that's controlling the mux/demux for your SCL. In the docs I have, I can't find any information about "S1" ... so I'm wondering if it's even on the board. Anyway ... might be worth a look.

 

Regards,

--Scott

 

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Participant ejubenville
Participant
813 Views
Registered: ‎10-17-2008

Re: Cadence I2C timeouts on PicoZed, no pin activity

I'm probing MIO 50 and 51 on our custom baseboard at the point connected to the PicoZed JX3 pins 66 and 64 (MIO 50 and 51, respectively).  

 

I can't find the S1 switch you are referring to on the PicoZed schematic.  I'm using the PicoZed 7015/7030 Rev C04.

 

http://zedboard.org/sites/default/files/documentations/PicoZed_7015_7030_Rev_C.PDF

 

I also have a MicroZed that I am willing to build a custom project for to verify I can see I2C activity with my kernel configuration, etc.  I have to dig up an example.

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Contributor
Contributor
809 Views
Registered: ‎04-04-2018

Re: Cadence I2C timeouts on PicoZed, no pin activity

Uugghh ... sorry for the distraction ... I was looking at the picoZed SDR schematic, my apologies.

 

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