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haberlan2
Observer
Observer
10,477 Views
Registered: ‎08-11-2015

Can access PL register from u-boot but not petalinux

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I can successfully access registers using the 'md' u-boot command after downloading u-boot.elf and bitstream using xmd.

 

When I download the image.ub and dtb using tftp, and boot petalinux, devmem and peek both lock up the board when accessing the same register.

 

The IP packager wasn't used to for the custom IP - they it's all vhdl.  Only thing that shows up in block diagram is an axi interface, the address of which shows up in xsdk.  Also haven;t added anything other than the PHY to the device tree - didn't think was required unless I wanted use the UIO driver or my own module.  Thought the axi slave would be accessible using peek or devmem without modifying the device tree. 

 

What am I doing wrong?

 

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rjsefton
Explorer
Explorer
17,711 Views
Registered: ‎11-25-2014

Check that the clock from the PS to the PL is enabled (FCLK0 most likely). For some reason Linux likes to disable the PS-PL clocks, even though they're enabled in the FSBL. Our software person has had to trudge through that a couple of times already.

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5 Replies
rjsefton
Explorer
Explorer
17,712 Views
Registered: ‎11-25-2014

Check that the clock from the PS to the PL is enabled (FCLK0 most likely). For some reason Linux likes to disable the PS-PL clocks, even though they're enabled in the FSBL. Our software person has had to trudge through that a couple of times already.

View solution in original post

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milosoftware
Scholar
Scholar
10,372 Views
Registered: ‎10-26-2012

If the clock is the problem, add "fclk-enable = <0xf>;" to the "clkc" node (inside slcr) of the devicetree. This will enable all four PS-PL clocks.

 

Problem is that no driver claims the clock, so the kernel switches them off to save power.

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haberlan2
Observer
Observer
10,248 Views
Registered: ‎08-11-2015

Yes, it was fclk.  I had already read several postings about fclk and had verified that it was enabled in slcr clkc entry.  Unfortunately, I didn't notice until much later that it was being disabled in the pcw.dtsi device tree file.  That one did the trick.

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ronnywebers
Advisor
Advisor
7,234 Views
Registered: ‎10-10-2014

interesting - could you please clarify 'who' can actually change the FCLK clocks (enable, set/modify frequency/ ...), is it the FSBL, u-boot, kernel and/or RFS?

 

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jeffdaq
Explorer
Explorer
7,217 Views
Registered: ‎11-22-2015

I know if you enable the fclk in vivado it will appear in the hdf and the hdf is used to generate the FSBL and the devicetree.  And you don't have to have it, I have a PCIe endpoint design that does not have fclk enabled because is use the PCIe refclk.

 

jeff