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Participant
Participant
2,338 Views
Registered: ‎08-28-2018

Cannot find device "eth0" in custom board (zynqmp/petalinux)

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Hi All:

We recently debug our custom board which used the chip XCZU4EV, there are two gems in the board(gem0 and gem1).

We use the phy chip ti dp83867, the same as the zcu104 Development kit.

We use the petalinux2018.2 to generate the boot files (boot.bin and image.ub) for sdcard boot.

To fit our boader I do the following works :

1. modify the device tree (named c0.dtsi) according the zcu104-revc.dtsi.

2. copy the c0.dtsi to project-spec/meta-user/recipes-bsp/device-tree/files/

3. add the /include/ "c0.dtsi" to the file system-user.dtsi, and add the SRC_URI += "file://c0.dtsi" to the file device-tree.bbappend

4. build the project and copy the boot file to sdcard.

but when boot from the sdcard, the uart prints "Configuring network interfaces... Cannot find device "eth0" in kernel stage, then I run the "ifconfig -a" and it only shows lo and sit0.

To locate the problem, I try to ping the pc in the uboot stage, and it succeed. so I guess there are something wrong in the device tree, Can someone tell me how to modify the device tree or solve the problem.(the c0.dtsi as shown below)

// SPDX-License-Identifier: GPL-2.0+
/*
 * dts file for Xilinx ZynqMP ZCU104
 *
 * (C) Copyright 2017 - 2018, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */

/ {
	model = "ZynqMP ZCU104 RevC";
	compatible = "xlnx,zynqmp";

};

&gem0 {
	phy-handle = <&phy0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gem0_default>;
	phy0: phy@c {
		reg = <0xc>;
		ti,rx-internal-delay = <0x8>;
		ti,tx-internal-delay = <0xa>;
		ti,fifo-depth = <0x1>;
		ti,rxctrl-strap-worka;
	};
};


&gem1 {
	phy-handle = <&phy1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gem1_default>;
	phy1: phy@c {
		reg = <0xc>;
		ti,rx-internal-delay = <0x8>;
		ti,tx-internal-delay = <0xa>;
		ti,fifo-depth = <0x1>;
		ti,rxctrl-strap-worka;
	};
};



&pinctrl0 {
	status = "okay";

	pinctrl_gem0_default: gem0-default {
		mux {
			function = "ethernet0";
			groups = "ethernet0_0_grp";
		};

		conf {
			groups = "ethernet0_0_grp";
			slew-rate = <1>;
			io-standard = <1>;
			drive-strength = <12>;
		};

		conf-rx {
			pins = "MIO32", "MIO33", "MIO34", "MIO35", "MIO36",
									"MIO37";
			bias-high-impedance;
			low-power-disable;
		};

		conf-tx {
			pins = "MIO26", "MIO27", "MIO28", "MIO29", "MIO30",
									"MIO31";
			bias-disable;
			low-power-enable;
		};

		mux-mdio {
			function = "mdio0";
			groups = "mdio0_0_grp";
		};

		conf-mdio {
			groups = "mdio0_0_grp";
			slew-rate = <1>;
			io-standard = <1>;
			bias-disable;
		};
	};


	pinctrl_gem1_default: gem1-default {
		mux {
			function = "ethernet1";
			groups = "ethernet1_0_grp";
		};

		conf {
			groups = "ethernet1_0_grp";
			slew-rate = <1>;
			io-standard = <1>;
			drive-strength = <12>;
		};

		conf-rx {
			pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
									"MIO49";
			bias-high-impedance;
			low-power-disable;
		};

		conf-tx {
			pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
									"MIO43";
			bias-disable;
			low-power-enable;
		};

		mux-mdio {
			function = "mdio1";
			groups = "mdio1_0_grp";
		};

		conf-mdio {
			groups = "mdio1_0_grp";
			slew-rate = <1>;
			io-standard = <1>;
			bias-disable;
		};
	};

};
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Participant
Participant
2,294 Views
Registered: ‎08-28-2018

企业微信截图_15529865741553.png

I found the problem.

View solution in original post

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Participant
Participant
2,295 Views
Registered: ‎08-28-2018

企业微信截图_15529865741553.png

I found the problem.

View solution in original post

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Contributor
Contributor
945 Views
Registered: ‎05-24-2018
Hello, I got a similar error. Do you mind sharing how you solved the problem?
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