08-21-2019 04:51 PM
I am looking for a sample example to try chip scope/ILA with Petalinux to try and capture AXI interfaces.
Any tutorial link or guide would be of great help.
08-21-2019 11:55 PM
08-22-2019 01:12 PM - edited 08-22-2019 01:12 PM
This is not what I am looking at, I don't want to details on setting up Ethernet to capture details, what I am looking at the IPs that can be used to debug interfaces in the design and also have this communicated over the petalinux.
08-22-2019 03:32 PM
08-29-2019 08:12 PM
Still did nt find a answer, I just need a basic tutorial on how to use ILA or for that sake any other PL debug tool along with Petalinux.
10-22-2019 01:17 PM
Yes I was able to do, just include ILA as a regular IP block.
Than Export HDF and than go ahead with Building the design in petalinux and obtain BOOT.bin.
Once ready with SD card image connect your JTAG and also open the HW manager on a system that is talking to HW and run your design with required trigger patterns.
I will be compiling the steps in a simple doc and post here in some time.
10-23-2019 05:12 AM
11-24-2019 08:49 PM
I have a project run on zcu102. if run base on standalone. I can view chipscope with vivado.
Once I use that file .hdf to build petalinux and boot from SD CARD. In vivado, once open hardware manager, I cann't view chipscope:
Log from vivado:
INFO: [Labtools 27-1434] Device xczu9 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
How do solve?
Thanks and Brgs.
11-24-2019 09:10 PM
Thanks for reaching out to us.
Could you please try disabling the CPU IDLE and rebuild your petalinux project, and see if that helps in connecting to vivado HW manager?
You can diasble the CPU IDLE feature by either of these ways mentioned in AR:
11-24-2019 10:46 PM
Thanks for your reply.
I just try disable CPU idle PM support follow 3 methos as suggest. But still not have change. That file .hdf can view ILA chipscope with standalone but not with petalinux.
11-25-2019 12:34 AM
Just sth popped in my mind, did you use system ILA or ILA(Integrated Logic Analyzer) in your project? there are two ILA IP in Xilinx repositories.
Make sure you configured ILA properly (should be System ILA).
Which version of Vivado do you use? for 2017 and later CPU idle PM support should be disabled for earlier versions is not necessary.
please let me know if you sure configuration is okay.
11-25-2019 12:50 AM
11-26-2019 03:28 AM